Memory device and manufacturing method of the memory device

Patent metadata

Field	Value
Publication number	US-2025275136-A1
Application number	US-202418769617-A
Country	US
Kind code	A1
Filing date	Jul 11, 2024
Priority date	Feb 27, 2024
Publication date	Aug 28, 2025
Grant date	—

Abstract

A memory device according to an embodiment of the present disclosure includes a stack structure including a cell region and a contact region, a cell plug located in the cell region and including a channel layer, a support pillar located in the contact region and including a dummy channel layer, and a contact opening contacting the support pillar wherein a thickness of the dummy channel layer is greater than a thickness of the channel layer.

First claim

What is claimed is:

1 . A memory device, comprising:
a stack structure including a cell region and a contact region; a cell plug located in the cell region and including a channel layer; a support pillar located in the contact region and including a dummy channel layer; and a contact opening contacting the support pillar, wherein a thickness of the dummy channel layer is greater than a thickness of the channel layer.

2 . The memory device of claim 1 , wherein the contact opening is in contact with the dummy channel layer of the support pillar.

3 . The memory device of claim 1 , wherein the cell plug further comprises:
a memory layer surrounding the channel layer; and a gap fill layer in the channel layer.

4 . The memory device of claim 1 , wherein the support pillar further comprises:
a dummy memory layer surrounding the dummy channel layer; and a dummy gap fill layer in the dummy channel layer.

5 . The memory device of claim 4 , wherein the contact opening penetrates the dummy memory layer and is in direct contact with the dummy channel layer.

6 . The memory device of claim 1 , wherein the support pillar is substantially the same height as the cell plug.

7 . The memory device of claim 1 , wherein the channel layer and the dummy channel layer include substantially the same material.

8 . The memory device of claim 1 , wherein the stack structure includes a plurality of conductive layers spaced apart from each other in a vertical direction.

9 . The memory device of claim 8 , wherein the contact opening extends from an upper surface of the stack structure toward a first conductive layer among the plurality of conductive layers.

10 . The memory device of claim 9 , further comprising a contact plug in the contact opening,
wherein the contact plug is in contact with the first conductive layer.

11 . The memory device of claim 9 , further comprising a spacer extending along an inner side surface of the contact opening.

12 . The memory device of claim 11 , further comprising a contact plug in the contact opening,
wherein the spacer separates conductive layers disposed over the first conductive layer among the plurality of conductive layers and the contact plug from each other.

13 . The memory device of claim 11 , further comprising a contact plug in the contact opening,
wherein the spacer spaces apart the dummy channel layer from the contact plug.

Assignees

• Sk Hynix Inc

Inventors

• Park In Su
• Choi Won Geun

Classifications

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title