Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2025275122-A1
Application number	US-202418918612-A
Country	US
Kind code	A1
Filing date	Oct 17, 2024
Priority date	Feb 23, 2024
Publication date	Aug 28, 2025
Grant date	—

Abstract

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises device isolation patterns in a substrate and defining active sections extending in a first direction, a first impurity region on a central region of the active section, second impurity regions on edges of the active section, a bit line connected to the first impurity region and running in a second direction across the active sections, a bit-line capping pattern on the bit line, a storage node contact in contact with each of the second impurity regions, a diffusion barrier pattern covering a top surface of the bit-line capping pattern and a top surface of the storage node contact, and a landing pad on the diffusion barrier pattern. A top surface of the diffusion barrier pattern is flat.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a plurality of device isolation patterns in a substrate, the device isolation patterns defining a plurality of active sections, the active sections extending in a first direction; a first impurity region on a central region of each of the active sections; a plurality of second impurity regions on edges of each of the active sections; a bit line connected to the first impurity region, the bit line running in a second direction across the active sections, the second direction intersecting the first direction; a bit-line capping pattern on the bit line; a storage node contact in contact with each of the second impurity regions; a diffusion barrier pattern covering a top surface of the bit-line capping pattern and a top surface of the storage node contact; and a landing pad on the diffusion barrier pattern, wherein a top surface of the diffusion barrier pattern is flat.

2 . The device of claim 1 , further comprising:
a bit-line spacer covering a sidewall of the bit line and a sidewall of the bit-line capping pattern, wherein a top surface of the bit-line spacer is flat, and wherein the top surface of the bit-line capping pattern is coplanar with the top surface of the bit-line spacer.

3 . The device of claim 2 , wherein
the diffusion barrier pattern includes a first part and a second part, the first part covers the top surface of the bit-line spacer and has a first thickness, and the second part covers an upper sidewall of the bit-line spacer and has a second thickness greater than the first thickness.

4 . The device of claim 3 , wherein
the diffusion barrier pattern further includes a third part beneath the second part, the third part covering a sidewall of the bit-line spacer, and the third part has a third thickness greater than the first thickness and less than the second thickness.

5 . The device of claim 3 , wherein the diffusion barrier pattern has the first thickness on the bit-line capping pattern.

6 . The device of claim 1 , wherein a lower end of the landing pad is at a level higher than a level of the top surface of the bit-line capping pattern.

7 . The device of claim 1 , wherein
the landing pad comprises a plurality of landing pads, the storage node contact comprises a plurality of storage node contacts, and the device further comprises a landing pad isolation pattern on the storage node contacts, respectively, and between adjacent pairs of the landing pads, respectively.

8 . The device of claim 1 , wherein the diffusion barrier pattern includes:
a first sub-diffusion barrier pattern covering a sidewall of the bit-line capping pattern; and a second sub-diffusion barrier pattern covering the top surface of the bit-line capping pattern and a sidewall of the first sub-diffusion barrier pattern, wherein the first sub-diffusion barrier pattern and the second sub-diffusion barrier pattern include different materials from each other.

9 . The device of claim 1 , further comprising:
a bit-line spacer covering a sidewall of the bit line and a sidewall of the bit-line capping pattern, wherein the bit-line spacer includes
a first sub-spacer covering the sidewall of the bit line
a second sub-spacer covering a lower sidewall of the first sub-spacer and exposing an upper sidewall of the first sub-spacer and
a third sub-spacer covering a sidewall of the second sub-spacer.

10 . A semiconductor device, comprising:
a plurality of device isolation patterns in a substrate, the device isolation patterns defining a plurality of active sections, the active sections extending in a first direction; a plurality of word lines in the substrate, the word lines running in a second direction across the active sections, the second direction intersecting the first direction; a first impurity region on a central region of each of the active sections; a plurality of second impurity regions on edges of each of the active sections; a bit line connected to the first impurity region, the bit line running in the second direction across the word lines; a bit-line capping pattern on the bit line; a bit-line spacer covering a sidewall of the bit line and a sidewall of the bit-line capping pattern; a storage node contact in contact with each of the second impurity regions; a diffusion barrier pattern covering a top surface of the bit-line capping pattern, a top surface of the storage node contact, and a top surface and a sidewall of the bit-line spacer; and a landing pad on the diffusion barrier pattern, wherein the diffusion barrier pattern has a first thickness on the top surface of the bit-line capping pattern and a second thickness on the sidewall of the bit-line capping pattern, the second thickness being greater than the first thickness.

11 . The device of claim 10 , wherein
the top surface of the bit-line capping pattern is flat, the top surface of the bit-line spacer is flat, and wherein the top surface of the bit-line capping pattern is coplanar with the top surface of the bit-line spacer.

12 . The device of claim 10 , wherein the diffusion barrier pattern has the first thickness on the top surface of the bit-line spacer.

13 . The device of claim 10 , wherein the diffusion barrier pattern includes:
a first part on an upper sidewall of the bit-line spacer; and a second part beneath the first part and having the second thickness, wherein the first part has a third thickness greater than the second thickness.

14 . The device of claim 10 , wherein a portion of the diffusion barrier pattern that is on the bit-line capping pattern has a flat top surface.

15 . The device of claim 10 , wherein a top surface of the diffusion barrier pattern on the bit-line capping pattern has an uneven structure.

16 . The device of claim 10 , wherein the bit-line spacer includes:
a first sub-spacer covering the sidewall of the bit line; a second sub-spacer covering a lower sidewall of the first sub-spacer and exposing an upper sidewall of the first sub-spacer; and a third sub-spacer covering a sidewall of the second sub-spacer.

17 . A semiconductor device, comprising:
a plurality of device isolation patterns in a substrate, the device isolation patterns defining a plurality of active sections, the active sections extending in a first direction; a first impurity region on a central region of each of the active sections; a plurality of second impurity regions on edges of each of the active sections; a bit line connected to the first impurity region, the bit line running in a second direction across the active sections, the second direction intersecting the first direction; a bit-line capping pattern on the bit line; a bit-line spacer covering a sidewall of the bit line and a sidewall of the bit-line capping pattern; a storage node contact in contact with each of the second impurity regions; a first sub-diffusion barrier pattern covering a top surface of the storage node contact and a sidewall of the bit-line spacer; a second sub-diffusion barrier pattern covering the first sub-diffusion barrier pattern and a top surface of the bit-line capping pattern; and a landing pad on the first and second sub-diffusion barrier patterns.

18 . The device of claim 17 , wherein a top surface of the first sub-diffusion barrier pattern, the top surface of the bit-line capping pattern, and a top surface of the bit-line spacer are flat and coplanar with each other.

19 . The device of claim 17 , wherein the second su

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Yanghee
• Kim Sujeong
• Kim Hyukmin
• Park Changmin
• Bae Jin-Woo
• Jang Woohyuk
• Han Jin Soon
• Hwang Hyunsu

Classifications

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/482 Primary

  Bit lines · CPC title

• H10B12/0335 Primary

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/03

  Making the capacitor or connections thereto · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title