Memory including bit line pillar

Patent metadata

Field	Value
Publication number	US-2025267853-A1
Application number	US-202418625666-A
Country	US
Kind code	A1
Filing date	Apr 3, 2024
Priority date	Feb 15, 2024
Publication date	Aug 21, 2025
Grant date	—

Abstract

A memory may include a plurality of word lines formed of N layers, M word lines being arranged in each layer, among the plurality of word lines, where each of N and M is an integer of 2 or more; a plurality of bit line pillars; and a plurality of memory cells disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively. Among the plurality of word lines, two or more word lines of the plurality of word lines may be grouped and driven together.

First claim

What is claimed is:

1 . A memory comprising:
a plurality of word lines formed of N layers, M word lines being arranged in each layer, among the plurality of word lines, where each of N and M is an integer of 2 or more; a plurality of bit line pillars; and a plurality of memory cells disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively, wherein two or more word lines of the plurality of word lines are grouped and driven together.

2 . The memory of claim 1 , wherein, among the plurality of word lines, the grouped word lines word lines are included in a same layer.

3 . The memory of claim 2 , wherein the plurality of bit line pillars are mutually electrically connected while forming a group in units of L, where L is an integer of 2 or more.

4 . The memory of claim 3 , wherein, among the bit line pillars, bit line pillars intersecting the grouped word lines are not mutually electrically connected.

5 . The memory of claim 1 , wherein each of the plurality of memory cells includes a transistor and a capacitor.

6 . The memory of claim 1 , wherein a first-half of the plurality of bit line pillars are connected to first bit line sense amplifiers disposed on a first side in a direction perpendicular to the plurality of bit line pillars, and a second-half of the plurality of bit line pillars are connected to second bit line sense amplifiers disposed on a second side in the direction perpendicular to the plurality of bit line pillars.

7 . The memory of claim 1 , wherein the grouped word lines among the plurality of word lines are shorted to each other.

8 . The memory of claim 1 , wherein each of the plurality of bit line pillars is disposed to pass between two word lines in each of the N layers.

9 . A memory comprising:
a plurality of word lines; a plurality of bit lines; and a plurality of memory cells connected to one of the plurality of word lines and one of the plurality of bit lines, wherein two or more word lines of the plurality of word lines are grouped and driven together.

10 . The memory of claim 9 , wherein the grouped word lines include a first word line and a second word line, and
among the plurality of bit lines, first bit lines connected to memory cells connected to the first word line and second bit lines connected to memory cells connected to the second word line do not overlap each other.

11 . The memory of claim 9 , wherein each of the plurality of memory cells includes a transistor and a capacitor.

Assignees

• Sk Hynix Inc

Inventors

• Kim Dong Kyu
• Kim Youn Guk
• Em Ho Seok
• Won Hyung Sik
• Lee Jeong Jun
• Cheon Jun Ho

Classifications

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• H10B12/488

  Word lines · CPC title

• H10B12/482 Primary

  Bit lines · CPC title

• H10B12/50

  Peripheral circuit region structures · CPC title