Electronic package module and method for fabrication of the same
US-2024413067-A1 · Dec 12, 2024 · US
Stacked dies and methods for forming bonded structures
US2025266416A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2025266416-A1 |
| Application number | US-202519063203-A |
| Country | US |
| Kind code | A1 |
| Filing date | Feb 25, 2025 |
| Priority date | May 19, 2016 |
| Publication date | Aug 21, 2025 |
| Grant date | — |
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- Title
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- Abstract
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- First independent claim
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- CPC / IPC classifications
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Abstract
Official abstract text for this publication.
In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method for forming a bonded structure, the method comprising: mounting a first singulated integrated device die to a carrier; after mounting. thinning the first integrated device die; and providing a protective material comprising a first layer on an exposed surface of the first integrated device die.
Assignees
Inventors
Classifications
for supporting or gripping · CPC title
Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title
characterised by their composition, e.g. multilayer masks or materials · CPC title
Etching of wafers, substrates or parts of devices · CPC title
between stacked chips · CPC title
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Frequently asked questions
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- What does patent US2025266416A1 cover?
- In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated…
- Who is the assignee on this patent?
- Adeia Semiconductor Bonding Technologies Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W74/014. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Aug 21 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).