Multigate Device Structure with Engineered Cladding and Method Making the Same

Patent metadata

Field	Value
Publication number	US-2025266290-A1
Application number	US-202519067103-A
Country	US
Kind code	A1
Filing date	Feb 28, 2025
Priority date	Dec 6, 2021
Publication date	Aug 21, 2025
Grant date	—

Abstract

The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

First claim

What is claimed is:

1 . A method, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of a third semiconductor material on sidewalls of the active region; forming an isolation feature over the liner within the trench; performing a rapid thermal nitridation process, thereby converting a portion of the liner into a semiconductor nitride layer; and forming a cladding layer of a fourth semiconductor material over the semiconductor nitride layer.

2 . The method of claim 1 , further comprising forming a dielectric layer on the liner before the performing of the rapid thermal nitridation process.

3 . The method of claim 2 , further comprising removing the dielectric layer after the performing of the rapid thermal nitridation process and before the forming of the cladding layer.

4 . The method of claim 3 , wherein
the dielectric layer includes silicon oxide; and the removing the dielectric layer further includes performing a chemical oxide removal (COR) process, and performing a post heating treatment (PHT).

5 . The method of claim 4 , wherein
the COR process includes applying NH 3 and HF at a first temperature; and the PHT includes applying an annealing process at a second temperature greater than the first temperature.

6 . The method of claim 1 , wherein
the first semiconductor material is silicon; and the second semiconductor material is silicon germanium.

7 . The method of claim 1 , wherein
the third semiconductor material is silicon; the fourth semiconductor material is silicon germanium; and the semiconductor nitride layer is a silicon nitride layer.

8 . The method of claim 1 , wherein the forming of the cladding layer includes
depositing the cladding layer on the active region such that the cladding layer is separated from the semiconductor stack by the semiconductor nitride layer; and performing an anisotropic etching process to the cladding layer.

9 . The method of claim 8 , wherein
the depositing the cladding layer on the active region includes depositing the cladding layer with a first portion on the semiconductor nitride layer and a second portion on the liner; the first portion of the cladding layer has an amorphous structure; and the second portion of the cladding layer has a crystalline structure.

10 . The method of claim 1 , further comprising:
forming a dummy gate stack on the active region; forming source/drain (S/D) features on the active region and connecting to the first semiconductor layers; removing the dummy gate stacks, resulting in a gate trench in an interlayer dielectric (ILD) layer; performing an etching process in the gate trench to selectively remove the cladding layer and the second semiconductor layers; and forming a gate stack in the gate trench, the gate stack wrapping around each of the first semiconductor layers.

11 . A method, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the active region; forming an isolation feature over the liner within the trench; and forming a diffusion blocking layer on the sidewalls of the active region and on the isolation feature.

12 . The method of claim 11 , further comprising forming a cladding layer of the second semiconductor material on the diffusion blocking layer.

13 . The method of claim 12 , further comprising:
forming a dummy gate stack on the cladding layer; forming source/drain (S/D) features on the active region and connecting to the first semiconductor layers; removing the dummy gate stacks, resulting in a gate trench in an interlayer dielectric (ILD) layer; performing an etching process in the gate trench to selectively remove the cladding layer and the second semiconductor layers; and forming a gate stack in the gate trench, the gate stack wrapping around each of the first semiconductor layers.

14 . The method of claim 12 , wherein
the diffusion blocking layer includes a silicon oxide layer; the first semiconductor material is silicon; and the second semiconductor material is silicon germanium.

15 . The method of claim 14 , wherein the forming of the diffusion blocking layer further includes performing an in-situ carbon (ISC) process to form a carbon-rich dielectric layer on the silicon oxide layer.

16 . The method of claim 15 , wherein the performing an ISC process includes applying a precursor containing

17 . The method of claim 14 , further comprising performing a rapid thermal nitridation (RTN) process, thereby converting the liner into a silicon nitride layer.

18 . The method of claim 17 , further comprising removing the silicon oxide layer after the performing of the rapid thermal nitridation process and before the forming of the cladding layer, wherein the removing the dielectric layer includes
applying NH3 and HF at a first temperature; and applying a post heating treatment at a second temperature being greater than the first temperature.

19 . A method, comprising:
forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a silicon layer on sidewalls of the active region, thereby forming a liner; forming an isolation feature on the isolation feature in the trench; and etching to remove exposed portion of the liner above the isolation feature.

20 . The method of claim 19 , further comprising epitaxially growing a cladding layer of the second semiconductor material such that the cladding layer is selectively grown on the active region relative to the isolation feature, wherein the cladding layer is in a crystalline structure and is free from surfaces of the isolation feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shen Shu-Wen
• Peng Yuan-Ching
• Chen Chien-Hung
• Lin Jheng-Wei
• Yang Ji-Xuan
• Kuo Jiun-Ming

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6316

  Formation by nitridation, e.g. nitridation of the substrate · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title