Array Substrate, Display Panel, Driving Method for Display Panel, and Display Apparatus

Patent metadata

Field	Value
Publication number	US-2025261492-A1
Application number	US-202318992304-A
Country	US
Kind code	A1
Filing date	May 17, 2023
Priority date	May 17, 2023
Publication date	Aug 14, 2025
Grant date	—

Abstract

An array substrate includes sub-pixels, gate lines and data lines. The sub-pixels form pixel groups each including the first and second sub-pixels. The first sub-pixel includes a first transistor and a first electrode group including a first pixel electrode and a first commons electrode. The second sub-pixel includes a second transistor and a second electrode group including a second pixel electrode and a second common electrode. The gate lines form gate line groups each including a first gate line and a second gate line. At least part of the data lines each include: first data segments between a i-th column of sub-pixels and a (i+1)th column of sub-pixels, second data segments between a (i−j)-th column of sub-pixels and a (i−j-1)-th column of sub-pixels, and third segments. An overlapping are of the first pixel electrode and first common electrode equals that of the second pixel electrode and second common electrode.

First claim

1 . An array substrate, comprising:
a base substrate; a plurality of sub-pixels arranged in an array and disposed on the base substrate, the plurality of sub-pixels being arranged in E rows and F columns, wherein the plurality of sub-pixels form a plurality of pixel groups, each pixel group includes a first sub-pixel and a second sub-pixel, the first sub-pixel includes a first transistor and a first electrode group, and the second sub-pixel includes a second transistor and a second electrode group; the first electrode group and the second electrode group are arranged sequentially along a row direction; the first transistor and the second transistor are both located between the first electrode group and the second electrode group, and are respectively located on both ends of the pixel group along a column direction; and the first electrode group includes a first pixel electrode and a first common electrode, and the second electrode group includes a second pixel electrode and a second common electrode; a plurality of gate lines disposed on the base substrate, the plurality of gate lines forming a plurality of gate line groups, wherein each gate line group includes a first gate line and a second gate line, and the first sub-pixel and the second sub-pixel of each pixel group are respectively connected to a first gate line and a second gate line of one gate line group; and a plurality of data lines disposed on the base substrate, wherein the first sub-pixel and the second sub-pixel of each pixel group are connected to one of the data lines; at least part of the plurality of data lines each include third data segments extending along the row direction, first data segments and second data segments extending along the column direction, a third data segment being connected between a first data segment and a second data segment; and the first data segments are disposed between an i-th column of sub-pixels and a (i+1)-th column of sub-pixels, and the second data segments are disposed between a (i−j)-th column of sub-pixels and a (i−j−1)-th column of sub-pixels, and j is greater than or equal to 1; and i+1≤F; wherein an overlapping area of the first pixel electrode and the first common electrode is equal to an overlapping area of the second pixel electrode and the second common electrode.

2 . The array substrate according to claim 1 , wherein j=1; and
two data lines located outermost in the row direction are a first data line and a second data line, wherein first data segments of the first data line are disposed between a first column of sub-pixels and a second column of sub-pixels, and second data segments of the first data line are disposed on a side of the first column of sub-pixels away from multiple columns of sub-pixels other than the first column of sub-pixels in the F columns; and first data segments of the second data line are disposed on a side of an F-th column of sub-pixels away from multiple columns of sub-pixels other than the F-th column of sub-pixels in the F columns, and second data segments of the second data line are disposed between a (F−1)-th column of sub-pixels and the F-th column of sub-pixels.

3 . The array substrate according to claim 1 , wherein at least a portion of the data line connected to the pixel group is located between the first electrode group and the second electrode group of the pixel group, and the at least a portion of the data line is a first data segment or a second data segment;
a first electrode of the first transistor and a first electrode of the second transistor are both connected to the data line, a second electrode of the first transistor is connected to the first pixel electrode, and a second electrode of the second transistor is connected to the second pixel electrode; and a direction that is from the first electrode to the second electrode of the first transistor and parallel to the row direction is a first direction, and a direction that is from the first electrode to the second electrode of the second transistor and parallel to the row direction is a second direction, the first direction being opposite to the second direction.

4 . The array substrate according to claim 3 , wherein the first transistor and the second transistor each include a gate electrode, an active layer, and source-drain electrodes that are stacked in sequence, and the source-drain electrodes include the first electrode and the second electrode; and an orthographic projection of the active layer on the base substrate lies within an orthographic projection of the gate electrode on the base substrate, and at least a portion of an orthographic projection of each of the first electrode and the second electrode on the base substrate lies within the orthographic projection of the active layer on the base substrate; and
an orthographic projection of the first electrode is U-shaped, and an opening of the first electrode faces the second electrode.

5 . The array substrate according to claim 1 , wherein the first pixel electrode and the second pixel electrode are block electrodes, the first common electrode and the second common electrode are strip electrodes, and the first common electrode and the second common electrode each include a plurality of slits;
an aperture ratio of the first sub-pixel is equal to an aperture ratio of the second sub-pixel; and the first electrode group has a first domain region and a second domain region arranged along the column direction, and the second electrode group is has a third domain region and a fourth domain region arranged along the column direction; and the first domain region, the second domain region, the third domain region, and the fourth domain region have a same aperture ratio.

6 . The array substrate according to claim 1 , further comprising: first spacers, a first spacer being disposed on a side of the first transistor away from the base substrate, and second spacers, a second spacer being disposed on a side of the second transistor away from the base substrate, wherein
a center of an orthographic projection of the first spacer on the base substrate is offset a first distance in a third direction relative to a center of an orthographic projection of the first transistor on the base substrate, the third direction being a direction in which the first transistor points to the second transistor; and a center of an orthographic projection of the second spacer on the base substrate is offset a second distance in a fourth direction relative to a center of an orthographic projection of the second transistor on the base substrate, the fourth direction being a direction in which the second transistor points to the first transistor.

7 . The array substrate according to claim 6 , wherein the first distance is equal to the second distance.

8 . The array substrate according to claim 7 , wherein the orthographic projection of the first spacer on the base substrate has an overlap with the orthographic projections of the first pixel electrode and the second pixel electrode on the base substrate; and
the orthographic projection of the second spacer on the base substrate has an overlap with the orthographic projections of the first pixel electrode and the second pixel electrode on the base substrate.

9 . A display panel having a display area and a peripheral area, comprising:
the array substrate according to claim 1 , wherein the plurality of pixel groups are located in the display area; and at least one gate driving circuit disposed on the base substrate and located in the peripheral area, wherein a gate driving circuit includes N shift registers cascaded; wherein an output terminal of a shift register at an i-th stage is connected to an input terminal of a shift register at a (i+n)-th stage, a

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Bian Ruomei
• Jin Honggui
• Bi Hongsheng
• Liu Yang
• Duan Zhilong
• Wang Peipei
• Sun Pingyuan
• Wang Jian
• Zhang Yong
• Yang Yue

Classifications

• H10H29/32

  characterised by the geometry or arrangement of elements within a subpixel, e.g. arrangement of the transistor within its RGB subpixel · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title