Physical unclonable function circuit, security circuit having the same, and method of operating the same

Patent metadata

Field	Value
Publication number	US-2025259664-A1
Application number	US-202418796957-A
Country	US
Kind code	A1
Filing date	Aug 7, 2024
Priority date	Feb 8, 2024
Publication date	Aug 14, 2025
Grant date	—

Abstract

A physical unclonable function (PUF) circuit is implemented using a Magnetoresistive Random Access Memory (MRAM) and generating an internal magnetic field to reduce a stray field of target cells. A random number is generated in the target cell by controlling a voltage applied to the target cells.

First claim

1 . A method of operating a physical unclonable function circuit using Magnetoresistive Random Access Memory (MRAM), comprising:
generating an internal magnetic field to reduce a stray field of target cells; and generating a random number in the target cells by controlling a voltage applied to the target cells.

2 . The method of claim 1 , wherein the MRAM is a Spin-Orbit Torque Magnetoresistive Random-Access Memory (SOT-MRAM).

3 . The method of claim 1 , wherein the MRAM includes a plurality of variable resistance cells,
wherein each of the plurality of variable resistance cells comprises: a SOT line connected to a corresponding source line, wherein the SOT line is configured to be provided with a wordline voltage; a free layer formed on top of the SOT line; a tunnel barrier formed on top of the free layer; and a pinned layer formed on top of the tunnel barrier and having a fixed spin direction, and wherein the target cells are some of the plurality of variable resistance cells.

4 . The method of claim 3 , wherein the generating of the internal magnetic field includes applying a predetermined voltage to an adjacent SOT line, wherein the adjacent SOT line corresponds to a variable resistance cell adjacent to the target cells among the plurality of variable resistance cells.

5 . The method of claim 4 , wherein the generating a random number in the target cells generating of the internal magnetic field further comprises applying a write voltage to a target SOT line, wherein the target SOT line corresponds to the target cells, and
wherein the predetermined voltage is lower than the write voltage.

6 . The method of claim 3 , wherein each of the plurality of variable resistance cells further comprises a digit line below the SOT line.

7 . The method of claim 6 , wherein the generating of the internal magnetic field comprises applying a voltage to the digit line, wherein the digit line corresponds to a variable resistance cell adjacent to the target cells among the plurality of variable resistance cells.

8 . The method of claim 7 , wherein the generating a random number in the target cells further comprises applying a write voltage to a target SOT line, wherein the target SOT line corresponds to the target cells.

9 . The method of claim 1 , wherein the MRAM comprises a plurality of variable resistance cells,
wherein each of the plurality of variable resistance cells comprises: a digit line; a SOT line formed above the digit line, connected to a corresponding source line, wherein the SOT line is configured to be provided with a wordline voltage; a free layer formed on top of the SOT line; a tunnel barrier formed on top of the free layer; and a pinned layer formed on top of the tunnel barrier, connected to a corresponding bitline, and having a fixed spin direction, and wherein the target cells are some of the plurality of variable resistance cells.

10 . The method of claim 9 , wherein the generating of the internal magnetic field comprises applying a voltage to an adjacent digit line, wherein the adjacent digit line corresponds to a variable resistance cell adjacent to the target cells among the plurality of variable resistance cells, and
wherein the generating a random number in the target cells comprises applying a write voltage to a target SOT line, wherein the target SOT line corresponds to the target cells.

11 . A physical unclonable function circuit comprising:
a plurality of variable resistance cells, wherein each of the plurality of variable resistance cells comprises: a Spin-Orbit Torque (SOT) line (SOT line) connected to a corresponding source line, wherein the SOT line is configured to be provided with a wordline voltage; a free layer formed on top of the SOT line; a tunnel barrier formed on top of the free layer; and a pinned layer formed on top of the tunnel barrier, and wherein a state of each of target cells may be determined in a state that an internal magnetic field is generated to reduce a stray field of the target cells among the plurality of variable resistance cells.

12 . The physical unclonable function circuit of claim 11 , wherein the internal magnetic field is generated by applying a predetermined voltage to an adjacent SOT line, wherein the adjacent SOT line corresponds to a variable resistance cell adjacent to the target cells.

13 . The physical unclonable function circuit of claim 11 , wherein each of the plurality of variable resistance cells further comprises a digit line below the SOT line, and
wherein the internal magnetic field is generated by applying a voltage to an adjacent digit line, wherein the adjacent digit line corresponds to a variable resistance cell adjacent to the target cells.

14 . The physical unclonable function circuit of claim 11 , further comprising:
a first switch configured to connect the pinned layer to a corresponding bitline based on a first switch signal during a read operation; and a second switch configured to connect the SOT line to the corresponding bitline based on a second switch signal during a write operation.

15 . The physical unclonable function circuit of claim 14 , wherein the SOT line is configured to be shared by at least two of the plurality of variable resistance cells.

16 . A security circuit comprising:
a physical unclonable function (PUF) circuit configured to generate a random number; and a processor configured to generate a key using the random number, wherein the PUF circuit comprises a PUF block, wherein the PUF block comprises a plurality of variable resistance cells connected to bitlines, source lines, read wordlines, and write wordlines, wherein each of the plurality of variable resistance cells comprises: a Spin-Orbit Torque (SOT) line (SOT line) connected to a corresponding source line among the source lines, wherein the SOT line is configured to be provided with a wordline voltage; a free layer formed above the SOT line; a tunnel barrier formed on top of the free layer; and a pinned layer formed on top of the tunnel barrier, and wherein a state of each of target cells may be determined in a state that an internal magnetic field is generated to reduce a stray field of the target cells among the plurality of variable resistance cells.

17 . The security circuit of claim 16 , wherein the PUF block further comprises:
a first switch configured to connect the pinned layer and a corresponding bitline among the bitlines based on to a first switch signal during a read operation; and a second switch configured to connect the SOT line and the corresponding bitline based on a second switch signal during a write operation.

18 . The security circuit of claim 17 , wherein the PUF circuit is configured to apply a write voltage to a target SOT line corresponding to the target cells, and to apply a predetermined voltage to an adjacent SOT line corresponding to a variable resistance cell adjacent to the target cells and generate the internal magnetic field, and
wherein the predetermined voltage is smaller than the write voltage.

19 . The security circuit of claim 16 , wherein at least two of the plurality of variable resistance cells include a shared digit line below the SOT line, and
wherein the PUF circuit is configured to apply a write voltage to a target SOT line corresponding to the target cells, and to apply a voltage to a digit line corresponding to a variable resistance cell adjacent to the target cells and generate the internal magnetic field.

20 . The security circ

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kilho
• Kim Daeshik
• Kim Yongjae

Classifications

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• G06F21/60

  Protecting data · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• G06F7/588

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G06F12/1425

  the protection being physical, e.g. cell, word, block · CPC title