Response to tamper detection in a memory device

Patent metadata

Field	Value
Publication number	US-9218509-B2
Application number	US-201414175063-A
Country	US
Kind code	B2
Filing date	Feb 7, 2014
Priority date	Feb 8, 2013
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.

First claim

What is claimed is:

1. A method comprising:
detecting a tamper-attempt indication corresponding to a memory device that includes an array of memory cells, wherein each memory cell in the array of memory cells is written to a first state using a first current flowing in a first direction through the memory cell and written to a second state using a second current flowing in a second direction through the memory cell, wherein the second direction is substantially opposite the first direction;
disabling a memory operation within the memory device based on the tamper-attempt indication, wherein the disabling includes adjusting a voltage corresponding to circuitry on the memory device used in the memory operation such that the memory operation is disabled; and
erasing data stored in the memory array in response to attempted performance of the memory operation that has been disabled, wherein the erasing data includes adjusting a first bias voltage corresponding to the first current such that the first current is inadequate to write the first state to the memory cell.

2. The method of claim 1 , wherein the adjusting the voltage includes adjusting at least one bias voltage used in write operations.

3. The method of claim 2 , wherein the at least one bias voltage corresponds to at least one of a column control bias voltage, a row control bias voltage, and a word line control bias voltage.

4. The method of claim 1 , wherein during normal operation a read operation uses the second current to write the second state to memory cells being accessed as a part of the read operation.

5. The method of claim 1 , wherein the adjusting the voltage includes adjusting at least one bias voltage used in read operations.

6. The method of claim 1 further comprises generating a mock current in response to an attempt to perform the memory operation that is disabled.

7. The method of claim 1 further comprises:
detecting an indication that the memory operation that has been disabled is to be enabled; and
restoring the voltage such that the memory operation is no longer disabled.

8. A method comprising:
detecting a tamper-attempt indication corresponding to a memory device that includes an array of memory cells;
disabling a memory operation within the memory device based on the tamper-attempt indication, wherein the disabling includes adjusting a voltage corresponding to circuitry on the memory device used in the memory operation such that the memory operation is disabled;
detecting an attempt to perform the memory operation that is disabled;
generating a mock current in response to the attempt to perform the memory operation that is disabled; and
erasing data stored in the memory array in response to detection of the attempt to perform the memory operation that has been disabled, wherein each memory cell in the array of memory cells is written to a first state using a first current flowing in a first direction through the memory cell, and wherein erasing data stored in the memory array further comprises adjusting a first bias voltage corresponding to the first current such that the first current is inadequate to write the first state to the memory cell.

9. The method of claim 8 , wherein adjusting the voltage includes adjusting at least one bias voltage used in write operations.

10. The method of claim 9 further comprising:
detecting an indication that the memory operation that has been disabled is to be enabled; and
restoring the at least one bias voltage such that the memory operation is no longer disabled.

11. The method of claim 8 , wherein each memory cell in the array of memory cells is written to a second state using a second current flowing in a second direction through the memory cell, wherein the second direction is substantially opposite the first direction.

12. The method of claim 8 , wherein generating the mock current further comprises generating the mock current such that a magnitude of the mock current approximates a magnitude of current that is generated by circuitry on the memory device during performance of the memory operation when the memory operation is not disabled.

13. The method of claim 8 , wherein generating the mock current further includes generating the mock current based at least in part on data associated with the memory operation that has been disabled.

14. The method of claim 8 , wherein generating a mock current further comprises performing a mock memory operation.

Assignees

• Everspin Technologies Inc

Inventors

• Alam Syed M
• Andre Thomas

Classifications

• G06F2221/2143

  Clearing memory, e.g. to prevent the data from being stolen · CPC title

• G06F21/79 Primary

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F21/78 Primary

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

• G06F21/86 Primary

  Secure or tamper-resistant housings · CPC title

• G06F3/062

  Securing storage systems · CPC title