Semiconductor device including stacked forksheet transistor structure with isolation wall

Patent metadata

Field	Value
Publication number	US-2025254988-A1
Application number	US-202418674073-A
Country	US
Kind code	A1
Filing date	May 24, 2024
Priority date	Feb 5, 2024
Publication date	Aug 7, 2025
Grant date	—

Abstract

Provided is a semiconductor device which includes: a 1 st source/drain pattern; a 2 nd source/drain pattern; an isolation wall between the 1 st source/drain pattern and the 2 nd source/drain pattern; a 1 st active contact on the 1 st source/drain pattern; and a 2 nd active contact on the 2 nd source/drain pattern, wherein the 1 st active contact contacts a 1 st side surface of the isolation wall, and the 2 nd active contact contacts a 2 nd side surface of the isolation wall, opposite to the 1 st sidewall.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a 1 st source/drain pattern; a 2 nd source/drain pattern; an isolation wall between the 1 st source/drain pattern and the 2 nd source/drain pattern; a 1 st active contact on the 1 st source/drain pattern; and a 2 nd active contact on the 2 nd source/drain pattern, wherein the 1 st active contact contacts a 1 st side surface of the isolation wall, and wherein the 2 nd active contact contacts a 2 nd side surface of the isolation wall, opposite to the 1 st sidewall.

2 . The semiconductor device of claim 1 , wherein the 1 st active contact and the 2 nd active contact are connected over a top surface of the isolation wall.

3 . The semiconductor device of claim 1 , further comprising:
a 1 st channel structure on the 1 st source/drain pattern; and a 2 nd channel structure on the 2 nd source/drain pattern, wherein the 1 st channel structure contacts the 1 st side surface of the isolation wall, and the 2 nd channel structure contacts the 2 nd side surface of the isolation wall.

4 . The 3D-stacked semiconductor device of claim 3 , wherein each of the 1 st channel structure and the 2 nd channel structure comprises a plurality of vertically stacked active layers.

5 . The semiconductor device of claim 3 , further comprising:
a 3 rd source/drain pattern above the 1 st source/drain region; and a 4 th source/drain pattern on above the 2 nd source/drain region, wherein the 3 rd source/drain pattern has a smaller width than the 1 st source/drain pattern, and the 4 th source/drain pattern has a smaller width than the 2 nd source/drain pattern.

6 . The semiconductor device of claim 5 , wherein the 1 st active contact is disposed between the 3 rd source/drain pattern and the isolation wall, and the 2 nd active contact is disposed between the 4 th source/drain pattern and the isolation wall.

7 . The semiconductor device of claim 5 , wherein the 1 st active contact contacts a top surface of the 1 st source/drain pattern which is not vertically overlapped by the 3 rd source/drain pattern.

8 . The semiconductor device of claim 7 , wherein the 2 nd active contact contacts a top surface of the 2 nd source/drain pattern which is not vertically overlapped by the 4 th source/drain pattern.

9 . The semiconductor device of claim 5 , further comprising:
a 3 rd channel structure on the 3 rd source/drain region; and a 4 th channel structure on the 4 th source/drain region, wherein the 3 rd channel structure has a smaller width than the 1 st channel structure, and the 4 th channel structure has a smaller width than the 2 nd channel structure.

10 . The semiconductor device of claim 9 , wherein a side surface of the 3 rd channel structure is vertically aligned with a side surface of the 1 st channel structure, and a side surface of the 4 th channel structure is vertically aligned with a side surface of the 2 nd channel structure.

11 . A semiconductor device comprising:
a 1 st source/drain pattern; a 1 st active contact on the 1 st source/drain pattern; and an isolation wall contacting the 1 st active contact.

12 . The semiconductor device of claim 11 , wherein the 1 st active contact contacts a side surface of the isolation wall.

13 . The semiconductor device of claim 11 , wherein the 1 st source/drain pattern contacts the isolation wall.

14 . The semiconductor device of claim 11 , further comprising a 1 st channel structure on the 1 st source/drain pattern,
wherein the 1 st channel structure and the 1 st source/drain pattern contact the isolation wall.

15 . The semiconductor device of claim 11 , further comprising:
a 2 nd source/drain pattern; and a 2 nd active contact, wherein the 2 nd active contact contacts the isolation wall.

16 . The semiconductor device of claim 11 , further comprising:
a 2 nd source/drain pattern; and wherein the 1 st active contact contacts the 2 nd source/drain pattern.

17 . The semiconductor device of claim 16 , wherein the 1 st active contact contacts a side surface and a top surface of the isolation wall.

18 . A method of manufacturing a semiconductor device, the method comprising:
forming a channel structure on a substrate; forming a recess penetrating through the channel structure to divide the channel structure into a 1 st channel structure and a 2 nd channel structure; forming an isolation wall in the recess; forming a 1 st source/drain pattern on the 1 st channel structure; and forming a 1 st active contact contacting the isolation wall and the 1 st source/drain pattern.

19 . The method of claim 18 , further comprising:
forming a 2 nd source/drain pattern on the 2 nd channel structure; and forming a 2 nd active contact contacting the isolation wall and the 2 nd source/drain pattern.

20 . The method of claim 18 , wherein the 1 st source/drain pattern is formed to contact the 1 st active contact.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Panjae
• Yun Seungchan
• Yang Myung
• Seo Kang-Ill

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D88/01 Primary

  Manufacture or treatment · CPC title

• H10D30/0191

  forming stacked channels, e.g. changing their shapes or sizes · CPC title

• H10D30/501

  FETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title