Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2025253221-A1
Application number	US-202519191053-A
Country	US
Kind code	A1
Filing date	Apr 28, 2025
Priority date	Sep 9, 2020
Publication date	Aug 7, 2025
Grant date	—

Abstract

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

First claim

What is claimed is:

1 . A method of fabricating a semiconductor package, the method comprising:
forming a redistribution substrate; mounting a semiconductor device on the redistribution substrate; and bonding an external connection terminal to the redistribution substrate, wherein the forming the redistribution substrate includes
sequentially stacking a release layer and an etch stop layer on a carrier substrate,
coating a first dielectric layer on the etch stop layer,
exposing and developing the first dielectric layer so that the first dielectric layer defines a first hole therein that exposes the etch stop layer,
sequentially stacking a sacrificial pattern and a wetting layer in the first hole, the wetting layer exposing an upper portion of an inner sidewall of the first hole,
forming a first barrier/seed layer and an under-bump on the wetting layer, and
removing the carrier substrate, the release layer, the etch stop layer, and the sacrificial pattern to expose a bottom surface of the wetting layer and a bottom surface of the first dielectric layer,
wherein the external connection terminal is bonded to the wetting layer.

2 . The method of claim 1 , wherein, before the sequentially stacking the sacrificial pattern and the wetting layer in the first hole, the forming the redistribution substrate further includes curing the first dielectric layer to incline the inner sidewall of the first hole.

3 . The method of claim 1 , wherein the forming the first barrier/seed layer and the under-bump on the wetting layer includes:
conformally forming the first barrier/seed layer on the first dielectric layer and the wetting layer; forming on the first barrier/seed layer a mask pattern, the mask pattern defining an opening that overlaps the first hole; forming the under-bump in the opening and the first hole; removing the mask pattern to expose the under-bump and the first barrier/seed layer that is adjacent the under-bump; and removing the first barrier/seed layer that is adjacent the under-bump to expose a top surface of the first dielectric layer.

4 . The method of claim 3 , wherein a width of the opening is greater than a width of the first hole in a direction parallel to the top surface of the first dielectric layer,
wherein the under-bump includes a first bump portion in the first hole and a second bump portion in the opening.

5 . The method of claim 1 , wherein, before separating the carrier substrate from the release layer during the removing the carrier substrate, the release layer, the etch stop layer and the sacrificial pattern, the forming the redistribution substrate further includes:
forming a second dielectric layer that covers the first dielectric layer; and forming a redistribution pattern that penetrates the second dielectric layer and is connected to the under-bump.

6 . The method of claim 5 , wherein the under-bump is in direct contact with the second dielectric layer, and wherein the first barrier/seed layer is not interposed between the second dielectric layer and the under-bump.

7 . The method of claim 6 , wherein the forming the second dielectric layer includes forming a metal oxide layer between the second dielectric layer and the under-bump.

8 . The method of claim 7 , wherein the forming the metal oxide layer includes forming the metal oxide layer as defining a void region between the metal oxide layer and the under-bump.

9 . The method of claim 1 , wherein the sacrificial pattern includes a conductive material having an etch selectivity with respect to both the etch stop layer and the wetting layer.

10 . A method of fabricating a semiconductor package, the method comprising:
forming a redistribution substrate; and bonding an external connection terminal to the redistribution substrate, wherein the forming the redistribution substrate includes
forming an etch stop layer on a carrier substrate,
coating a first dielectric layer on the etch stop layer,
exposing and developing the first dielectric layer so that the first dielectric layer defines a first hole penetrating the first dielectric layer,
sequentially stacking a sacrificial pattern and a wetting layer in the first hole, the wetting layer exposing an upper portion of an inner sidewall of the first hole,
forming a first barrier/seed layer and an under-bump on the wetting layer, and
exposing a bottom surface of the wetting layer and a bottom surface of the first dielectric layer,
wherein the forming the first barrier/seed layer and the under-bump includes
forming the first barrier/seed layer conformally covering a top surface of the first dielectric layer, an exposed upper portion of an inner sidewall of the first hole and a top surface of the wetting layer, and
forming the under-bump on the first barrier/seed layer.

11 . The method of claim 10 , wherein the forming the etch stop layer on the carrier substrate includes:
forming a release layer on the carrier substrate; and stacking the etch stop layer on the release layer.

12 . The method of claim 11 , wherein the exposing the bottom surface of the wetting layer and the bottom surface of the first dielectric layer includes:
removing the carrier substrate and the release layer; and removing the etch stop layer and the sacrificial pattern.

13 . The method of claim 10 , wherein, before the sequentially stacking the sacrificial pattern and the wetting layer in the first hole, the forming the redistribution substrate further includes curing the first dielectric layer to incline the inner sidewall of the first hole, and
wherein the inner sidewall of the first hole and a bottom surface of the first dielectric layer form an acute angle.

14 . The method of claim 10 , wherein the forming the first barrier/seed layer and the under-bump on the wetting layer includes:
conformally forming the first barrier/seed layer on the first dielectric layer and the wetting layer; forming on the first barrier/seed layer a mask pattern, the mask pattern defining an opening therein that overlaps the first hole; forming the under-bump in the opening and the first hole; removing the mask pattern to expose the under-bump and the first barrier/seed layer that is adjacent the under-bump; and removing the first barrier/seed layer that is adjacent the under-bump to expose the top surface of the first dielectric layer, wherein a width of the opening is greater than a width of the first hole in a direction parallel to the top surface of the first dielectric layer, and wherein the under-bump includes a first bump portion in the first hole and a second bump portion in the opening.

15 . The method of claim 11 , wherein the forming the redistribution substrate further comprises separating the carrier substrate from the release layer, and
wherein before the separating the carrier substrate from the release layer, the forming the redistribution substrate further includes: forming a second dielectric layer that covers the first dielectric layer and the under-bump; and forming a metal oxide layer between the second dielectric layer and the under-bump, the forming the metal oxide layer comprises forming the metal oxide layer as defining a void region between the metal oxide layer and the under-bump.

16 . A method of fabricating a semiconductor package, the method comprising:
forming a redistribution substrate; and bonding an external connection terminal to the redistribution substrate, wherein the forming the redistribution substrate includes
forming an etch stop layer on a carrier substrate,
coating a first diel

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Gwangjae
• Park Jung-Ho
• Lee Seokhyun
• Yoon Yaejung

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W90/722

  between stacked chips · CPC title