Multiplier Circuit with Carry-Based Partial Product Encoding

Patent metadata

Field	Value
Publication number	US-2025251910-A1
Application number	US-202418620683-A
Country	US
Kind code	A1
Filing date	Mar 28, 2024
Priority date	Feb 6, 2024
Publication date	Aug 7, 2025
Grant date	—

Abstract

Integrated circuit devices, methods, and circuitry for an efficient multiplier are provided. Multiplier circuitry to multiply a multiplicand value with a multiplier value may include, among other things, input circuitry and carry-based coding circuitry. The input circuitry may receive the multiplicand value and the multiplier value. The carry-based coding circuitry may receive bits of the multiplier value and generate multiplication codes using a carry-based coding scheme that includes multiplication codes according to a Booth's coding scheme but with at least one multiplication code that is removed and replaced with another at least one multiplication code with a different value. A first encoder of the carry-based coding circuitry may receive a carry signal to adjust a multiplication code value of the first encoder based on a second encoder of the carry-based coding circuitry encoding the multiplication code with the different value.

First claim

What is claimed is:

1 . Multiplier circuitry to multiply a multiplicand value with a multiplier value, the multiplier circuitry comprising:
input circuitry to receive the multiplicand value and the multiplier value; and carry-based coding circuitry to receive bits of the multiplier value and generate multiplication codes using a carry-based coding scheme that includes multiplication codes according to a Booth's coding scheme but with at least one multiplication code that is removed and replaced with another at least one multiplication code with a different value, wherein a first encoder of the carry-based coding circuitry receives a carry signal to adjust a multiplication code value of the first encoder based on a second encoder of the carry-based coding circuitry encoding the multiplication code with the different value.

2 . The multiplier circuitry of claim 1 , wherein the carry-based coding circuitry comprises at least one encoder to generate at least four different multiplication codes when the Booth's coding scheme is to generate at least five different multiplication codes.

3 . The multiplier circuitry of claim 2 , wherein the Booth's coding scheme is to generate multiplication codes corresponding to at least 0, 1, −1, 2, and −2 and the at least one encoder of the carry-based coding circuitry is to generate at least 0, 1, −1, and 2, but not −2.

4 . The multiplier circuitry of claim 2 , wherein the Booth's coding scheme is to generate multiplication codes corresponding to at least 0, 1, −1, 2, and −2 and the at least one encoder of the carry-based coding circuitry is to generate at least 0, 1, 2, and −2, but not −1.

5 . The multiplier circuitry of claim 1 , wherein the other at least one multiplication code with the different value comprises the only multiplication code in which the carry signal is not equal to an input bit received from the multiplier value.

6 . The multiplier circuitry of claim 1 , wherein the encoders of the carry-based coding circuitry comprise a sequence of carry-based encoders to generate respective multiplication codes, wherein the respective multiplication codes are generated based on respective portions of the bits and the carry value corresponding to a previously generated multiplication code generated by a previous carry-based encoder in the sequence.

7 . The multiplier circuitry of claim 6 , comprising a prefix tree to generate carry values to provide to at least some of the sequence of carry-based encoders.

8 . The multiplier circuitry of claim 7 , wherein the prefix tree comprises a Sklansky, Brent-Kung, Kogge-Stone, Ladner-Fisher, or Han-Carson prefix tree.

9 . The multiplier circuitry of claim 1 , comprising carry-less coding circuitry to receive other bits of the multiplier value and generate other multiplication codes using a carry-less coding scheme that includes multiplication codes according to the Booth's coding scheme or a different Booth's coding scheme.

10 . The multiplier circuitry of claim 9 , wherein the carry-less coding circuitry is to generate the other multiplication codes according to a Booth's radix 4 coding scheme or a Booth's radix 8 coding scheme.

11 . The multiplier circuitry of claim 9 , wherein a next encoder of the carry-less coding circuitry after a previous encoder of the carry-based coding circuitry uses a carry out of the previous encoder of the carry-based coding circuitry as a least significant bit of its coding scheme.

12 . An integrated circuit comprising:
carry-based coding circuitry to receive a first portion of bits of a multiplier value and generate a first set of multiplication codes using a carry-based coding scheme; first partial product multiplexing circuitry to select partial products as a multiple of a multiplicand based on respective multiplication codes of the first set of multiplication codes provided by the carry-based coding circuitry; carry-less coding circuitry to receive a second portion of bits of the multiplier value and generate a second set of multiplication codes using a carry-less coding scheme; and second partial product multiplexing circuitry to select partial products as a multiple of the multiplicand based on respective multiplication codes of the second set of multiplication codes provided by the carry-less coding circuitry.

13 . The integrated circuit of claim 12 , wherein the carry-based coding circuitry and the carry-less coding circuitry are of different radices.

14 . The integrated circuit of claim 13 , wherein the carry-less coding circuitry is of a higher radix than the carry-based coding circuitry.

15 . The integrated circuit of claim 13 , wherein the carry-based coding circuitry is of radix 4.

16 . The integrated circuit of claim 13 , wherein the carry-less coding circuitry is of radix 8.

17 . The integrated circuit of claim 12 , comprising a prefix tree to generate carries for at least a subset of encoders of the carry-based coding circuitry.

18 . The integrated circuit of claim 17 , wherein the prefix tree is to generate a carry for a first encoder of the carry-less coding circuitry receiving the second portion of bits of the multiplier after the carry-based coding circuitry.

19 . A method comprising:
receiving a multiplicand (A) and multiplier (B) into multiplier circuitry; encoding a portion of the multiplier (B) to generate multiplication codes using a carry-based encoding scheme having some Booth's multiplication codes M that are found in a carry-less Booth's encoding scheme, but with at least one fewer multiplication code M than the carry-less Booth's encoding scheme; using a partial product multiplexer to select partial products based on the multiplication codes generated using the carry-based encoding scheme; and adding the partial products to obtain a product of the multiplicand (A) multiplied by the multiplier (B).

20 . The method of claim 19 , wherein the at least one multiplication code M that is removed from the carry-less Booth's encoding scheme is replaced with an existing multiplication code M but using a different a carry-out value for that coding.

Assignees

• Altera Corp

Inventors

• Kucherenko Igor Viktorovich
• Pasca Bogdan
• Langhammer Martin

Classifications

• G06F7/523 Primary

  Multiplying only · CPC title

• G06F7/5336 Primary

  overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm · CPC title