Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025248110-A1
Application number	US-202519185109-A
Country	US
Kind code	A1
Filing date	Apr 21, 2025
Priority date	Sep 8, 2021
Publication date	Jul 31, 2025
Grant date	—

Abstract

A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity. The third structure includes third lower and upper impurity regions having the second-type conductivity, the third upper impurity region having an impurity concentration higher than a that of the third lower impurity region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first device including first active regions spaced apart from each other on a substrate, and a first structure, a second structure, and a third structure on each of the first active regions; and a second device including a second active region spaced apart from the first active regions on the substrate and extending in a first direction parallel to an upper surface of the substrate, at least one gate structure intersecting the second active region and extending in a second direction, a source/drain region including a lower source/drain region on the second active region on at least one side of the gate structure and having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity different from the first-type conductivity, wherein: the first structure includes a first lower impurity region and a first upper impurity region on the first lower impurity region, the second structure includes a second impurity region having the first-type conductivity, and the third structure includes a third lower impurity region having the second-type conductivity.

2 . The semiconductor device as claimed in claim 1 , wherein the third structure further includes a third upper insulating layer on the third lower impurity region.

3 . The semiconductor device as claimed in claim 2 , wherein the third upper insulating layer includes the same material as a material of the inter-source/drain region insulating layer.

4 . The semiconductor device as claimed in claim 1 , wherein the third structure further includes a third upper impurity region on the third lower impurity region having the second-type conductivity, and having an impurity concentration higher than an impurity concentration of the third lower impurity region.

5 . The semiconductor device as claimed in claim 4 , wherein:
the third lower impurity region includes a stack structure of first semiconductor layers and second semiconductor layers alternately stacked, the third upper impurity region includes a third semiconductor layer, the third semiconductor layer includes a material different from a material of at least one of the first semiconductor layers and the second semiconductor layers, and a thickness of the third semiconductor layer is greater than a thickness of each of the first and second semiconductor layers.

6 . The semiconductor device as claimed in claim 4 , wherein:
the impurity concentration of the third lower impurity region is in a range of about 1×10 19 /cm 3 to 5×10 19 /cm 3 , and the impurity concentration of the third upper impurity region is in a range of about 1×10 20 /cm 3 to 5×10 20 /cm 3 .

7 . The semiconductor device as claimed in claim 1 , wherein the second structure further includes a second upper insulating layer on the second impurity region.

8 . The semiconductor device as claimed in claim 7 , wherein the second upper insulating layer includes a same material as a material of the inter-source/drain region insulating layer.

9 . The semiconductor device as claimed in claim 1 , wherein:
each of the first lower impurity region and the first upper impurity region has the second-type conductivity, the first lower impurity region includes a stack structure of first semiconductor layers and second semiconductor layers alternately stacked, the first semiconductor layers are first material layers, the second semiconductor layers are second material layers different from the first material layers, the first upper impurity region includes a third semiconductor layer configured as a third material layer, the third material layer is different from at least one of the first and second material layers, and a thickness of the third material layer is greater than a thickness of each of the first and second material layers.

10 . The semiconductor device as claimed in claim 1 , wherein:
an impurity concentration of the first lower impurity region is lower than an impurity concentration of the first upper impurity region, and the first lower impurity region is on substantially the same level as a level of the lower source/drain region.

11 . The semiconductor device as claimed in claim 1 , further comprising:
an emitter contact plug in contact with the first upper impurity region; a base contact plug in contact with the second impurity region; and a collector contact plug in contact with the third lower impurity region.

12 . The semiconductor device as claimed in claim 11 , wherein the base contact plug includes:
a horizontal contact plug connected to at least a portion of a side surface of the second impurity region; and a vertical contact plug not in contact with the second impurity region, and connected to the horizontal contact plug.

13 . The semiconductor device as claimed in claim 1 , further comprising dummy gate structures on upper surfaces of each of the second and third structures, respectively, the dummy gate structures extending and being spaced apart from the gate structure, wherein the dummy gate structures are not on the first structure.

14 . A semiconductor device, comprising:
a first device including a first structure, a second structure, and a third structure spaced apart from each other on a substrate; a second device including an active region extending in a first direction parallel to an upper surface of the substrate, at least one gate structure intersecting the active region and extending in a second direction, a source/drain region including a lower source/drain region on the active region on at least one side of the gate structure and having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity different from the first-type conductivity, wherein: the first structure includes a first impurity region having the first-type conductivity, the second structure includes a second lower impurity region having a stack structure of first and second semiconductor layers alternately stacked and having the second-type conductivity, and a second upper impurity region including a third semiconductor layer on the second lower impurity region and having the second-type conductivity, the first semiconductor layers are first material layers, the second semiconductor layers are second material layers different from the first material layers, the third semiconductor layer is a third material layer different from at least one of the first and second material layers, and the third structure includes a third impurity region having the first-type conductivity.

15 . The semiconductor device as claimed in claim 14 , wherein a thickness of the third material layer is greater than a thickness of each of the first and second material layers.

16 . The semiconductor device as claimed in claim 14 , further comprising:
an emitter contact plug in contact with the first impurity region; a base contact plug in contact with at least one of the second upper and lower impurity regions; and a collector contact plug in contact with the third impurity region.

17 . The semiconductor device as claimed in claim 14 , wherein an impurity concentration of the second lower impurity region is lower than an impurity concentration of the second upper impurity region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sungil
• Park Jaehyun
• Kim Hyo-Jin
• Kim Hyojin
• Ha Daewon

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10D84/0109

  the at least one component covered by H10D12/00 or H10D30/00 being a MOS device · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/281

  Base electrodes for bipolar transistors · CPC title

• H10D64/231

  Emitter or collector electrodes for bipolar transistors · CPC title