Electronic package and method of forming the same

Patent metadata

Field	Value
Publication number	US-2025246514-A1
Application number	US-202519183753-A
Country	US
Kind code	A1
Filing date	Apr 18, 2025
Priority date	Aug 6, 2021
Publication date	Jul 31, 2025
Grant date	—

Abstract

An electronic package is provided in the present disclosure. The electronic package comprises: a heat spreading component; a first electronic component disposed on the heat spreading component; and a second electronic component disposed on the first electronic component, wherein the second electronic component comprises an interconnection structure passing through the second electronic component and electrically connecting the first electronic component. In this way, through the use of the interconnection structure, the heat dissipation of the electronic components in the package can be improved. Also, through the use of the encapsulant, the stacked electronic components can be protected by the encapsulant so as to avoid being damaged.

First claim

What is claimed is:

1 . An electronic package, comprising:
a first electronic component; a second electronic component disposed under the first electronic component; and an encapsulant encapsulating the first electronic component and the second electronic component; wherein a first conductive interconnector is disposed on a bottom surface of the first electronic component, the bottom surface of the first electronic component facing the second electronic component, and wherein the first conductive interconnector is encapsulated by the encapsulant and exposed at a bottom surface of the encapsulant, wherein the first conductive interconnector extends from a height above the second electronic component to a height below the second electronic component.

2 . The electronic package of claim 1 , further comprising a third electronic component disposed under the second electronic component and encapsulated by the encapsulant, wherein the first conductive interconnector extends from a height above the third electronic component to a height below the third electronic component.

3 . The electronic package of claim 2 , wherein a second conductive interconnector is disposed on a bottom surface of the second electronic component, and wherein the second conductive interconnector is encapsulated by the encapsulant and exposed at the bottom surface of the encapsulant, wherein the second conductive interconnector extends from a height above the third electronic component to a height below the third electronic component.

4 . The electronic package of claim 3 , wherein a bottom surface of the first conductive interconnector and a bottom surface of the second conductive interconnector are substantially coplanar.

5 . The electronic package of claim 1 , further comprising a redistribution layer disposed on the encapsulant, wherein, in a cross-sectional view, an interconnection of the redistribution layer tapers towards the encapsulant.

6 . The electronic package of claim 3 , wherein the encapsulant does not extend over a top surface of the first electronic component.

7 . The electronic package of claim 6 , wherein a third conductive interconnector is disposed on a bottom surface of the third electronic component, and wherein the third conductive interconnector is encapsulated by the encapsulant and exposed at the bottom surface of the encapsulant, and wherein a bottom surface of the third conductive interconnector and a bottom surface of the second conductive interconnector are substantially coplanar.

8 . The electronic package of claim 6 , wherein a height of a top surface of the encapsulant, opposite to the bottom surface of the encapsulant, is above a height of the top surface of the first electronic component.

9 . An electronic package, comprising:
a first electronic component; a second electronic component disposed under the first electronic component and comprising a plurality of first interconnections passing through the second electronic component; a third electronic component is disposed under the second electronic component, wherein a width of the third electronic component is greater than a width of the second electronic component; and an encapsulant encapsulating the first electronic component, the second electronic component and the third electronic component, wherein the encapsulant does not extend over a top surface of the first electronic component.

10 . The electronic package of claim 9 , wherein, in a cross-sectional view, wherein a lateral surface of the first electronic component is not aligned with a lateral surface of the third electronic component in a direction substantially perpendicular to a bottom surface of the encapsulant.

11 . The electronic package of claim 10 , wherein, in the cross-sectional view, the encapsulant extends within a gap between the first electronic component and the second electronic component.

12 . The electronic package of claim 11 , wherein, in the cross-sectional view, the encapsulant further extends within a gap between the second electronic component and the third electronic component.

13 . The electronic package of claim 9 , wherein the third electronic component comprises a plurality of second interconnections passing through the third electronic component.

14 . The electronic package of claim 13 , wherein the first electronic component is electrically connected to the second electronic component through a first solder material, and wherein the encapsulant directly contacts the first solder material.

15 . The electronic package of claim 14 , wherein the second electronic component is electrically connected to the third electronic component through a second solder material, and wherein the encapsulant directly contacts the second solder material.

16 . An electronic package, comprising:
a first interposer; a second interposer disposed above the first interposer, wherein a width of the second interposer is less than a width of the first interposer; a first electronic component disposed over the second interposer; and a second electronic component disposed over the first interposer; wherein the second electronic component and the second interposer are disposed side by side.

17 . The electronic package of claim 16 , further comprising an encapsulant encapsulating the first electronic component, the second electronic component and the second interposer.

18 . The electronic package of claim 16 , wherein the first interposer comprises a first interconnection structure and the second interposer comprises a second interconnection structure.

19 . The electronic package of claim 16 , further comprising a first solder material disposed between the second electronic component and the first interposer and a second solder disposed between the second interposer and the first interposer.

20 . The electronic package of claim 17 , wherein the encapsulant does not extend over a top surface of the first electronic component.

Assignees

• Advanced Semiconductor Eng

Inventors

• Yen You-Lung
• Appelt Bernd Karl

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title