Vector Processor Architectures

Patent metadata

Field	Value
Publication number	US-2025238232-A1
Application number	US-202519071690-A
Country	US
Kind code	A1
Filing date	Mar 5, 2025
Priority date	Aug 28, 2020
Publication date	Jul 24, 2025
Grant date	—

Abstract

The present disclosure relates to an integrated circuit device that includes a plurality of vector registers configurable to store a plurality of vectors and switch circuitry communicatively coupled to the plurality of vector registers. The switch circuitry is configurable to route a portion of the plurality of vectors. Additionally, the integrated circuit device includes a plurality of vector processing units communicatively coupled to the switch circuitry. The plurality of vector processing units is configurable to receive the portion of the plurality of vectors, perform one or more operations involving the portion of the plurality of vector inputs, and output a second plurality of vectors generated by performing the one or more operations.

First claim

What is claimed is:

1 . A programmable logic device comprising:
a plurality of vector registers configurable to store a plurality of vectors; switch circuitry communicatively coupled to the plurality of vector registers, wherein the switch circuitry is configurable to route a portion of the plurality of vectors; a plurality of vector processing units implemented on one or more digital signal processing (DSP) blocks of the programmable logic device, wherein the plurality of vector processing units is communicatively coupled to the switch circuitry and configurable to receive the portion of the plurality of vectors; and control circuitry configurable to:
receive an instruction to perform an operation involving the portion of the plurality of vectors; and
cause the portion of the plurality of vectors to be routed from the plurality of vector registers to a first vector processing unit of the plurality of vector processing units.

2 . The programmable logic device of claim 1 , comprising one or more memory banks that store the plurality of vectors.

3 . The programmable logic device of claim 1 , comprising the control circuitry configurable to cause an output from the first vector processing unit to be written to the plurality of vector registers.

4 . The programmable logic device of claim 1 , wherein the operation comprises a vector-vector multiplication operation.

5 . The programmable logic device of claim 1 , wherein the operation comprises a vector addition operation.

6 . The programmable logic device of claim 1 , wherein the operation is a conditional operation.

7 . The programmable logic device of claim 6 , wherein the conditional operation comprises a greater than, less than, or equal to a condition.

8 . The programmable logic device of claim 7 , comprising a plurality of flag registers, wherein the programmable logic device is configurable to determine whether the condition of the conditional operation is present and, in response to determining the condition is present, generate a flag in the plurality of flag registers.

9 . The programmable logic device of claim 8 , wherein the programmable logic device is configurable to perform the operation, determine whether a flag corresponding to the operation is present in the plurality of flag registers, and refrain from writing a result of the operation to be written to the plurality of vector registers when the flag corresponding to the operation is present.

10 . The programmable logic device of claim 9 , wherein the programmable logic device is configurable to determine whether the flag is present prior to performing the operation.

11 . A vector processing system comprising:
one or more memory banks configurable to store a plurality of vectors; switch circuitry communicatively coupled to the one or more memory banks, wherein the switch circuitry is configurable to route a portion of the plurality of vectors; and a plurality of vector processing units communicatively coupled to the switch circuitry and configurable to receive the portion of the plurality of vectors; and control circuitry configurable to receive an instruction to perform an operation involving the portion of the plurality of vectors, and cause the portion of the plurality of vectors to be routed from the one or more memory banks to a first vector processing unit of the plurality of vector processing units.

12 . The vector processing system of claim 11 , wherein the plurality of vector processing units comprise a second vector processing unit, and wherein the first vector processing unit comprises first interconnect circuitry and the second vector processing unit comprises second interconnect circuitry.

13 . The vector processing system of claim 12 , wherein the first vector processing unit and the second vector processing unit are communicatively coupled to one another via the first interconnect circuitry and the second interconnect circuitry.

14 . The vector processing system of claim 12 , wherein the second vector processing unit is configurable to:
receive an output from the first vector processing unit; and perform the operation involving the output and a value from the portion of the plurality of vectors.

15 . The vector processing system of claim 14 , wherein the operation is a conditional operation, and wherein the conditional operation comprises a greater than, less than, or equal to a condition.

16 . The vector processing system of claim 15 , comprising a plurality of flag registers, wherein the vector processing system is configurable to determine whether the condition of the conditional operation is present and, in response to determining the condition is present, generate a flag in the plurality of flag registers.

17 . The vector processing system of claim 16 , wherein the vector processing system is configurable to perform the operation, determine whether a flag corresponding to the operation is present in the plurality of flag registers, and refrain from writing a result of the operation to be written to the one or more memory banks when the flag corresponding to the operation is present.

18 . An integrated circuit device comprising:
a plurality of vector registers configurable to store a plurality of vectors; and a plurality of vector processing units configurable to receive a portion of the plurality of vectors; and control circuitry configurable to:
receive an instruction to perform an operation involving the portion of the plurality of vectors; and
cause the portion of the plurality of vectors to be routed from the plurality of vector registers to a first vector processing unit of the plurality of vector processing units.

19 . The integrated circuit device of claim 18 , wherein the operation comprises a conditional operation, and wherein the conditional operation comprises a greater than, less than, equal to a condition.

20 . The integrated circuit device of claim 19 , comprising a plurality of flag registers, wherein the integrated circuit device is configurable to determine whether the condition of the conditional operation is present and, in response to determining the condition is present, generate a flag in the plurality of flag registers.

Assignees

• Altera Corp

Inventors

• Langhammer Martin
• Nurvitadhi Eriko
• Baeckler Gregg William

Classifications

• G06F9/30038

  using a mask · CPC title

• G06F9/38873

  Iterative single instructions for multiple data lanes [SIMD] · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F30/347

  Physical level, e.g. placement or routing · CPC title