Die-to-die probe pad connection in a stacked semiconductor device

Patent metadata

Field	Value
Publication number	US-2025226324-A1
Application number	US-202519011357-A
Country	US
Kind code	A1
Filing date	Jan 6, 2025
Priority date	Jan 9, 2024
Publication date	Jul 10, 2025
Grant date	—

Abstract

Methods, systems, and devices for die-to-die probe pad connection in a stacked semiconductor device are described. The stacked semiconductor device may include a first probe pad that is on a physically accessible surface of a stack of semiconductor dies. The stacked semiconductor device may include a second probe pad located at a physically inaccessible surface of (e.g., within) the stack of semiconductor dies. And the stacked semiconductor device may include a conductive path that electrically couples the first probe pad with the second probe pad.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first die comprising a first probe pad electrically coupled with a first through-silicon-via (TSV) that extends at least partially through the first die; a second die stacked with the first die and comprising a second probe pad that is positioned within the second die; and a conductive interconnect that electrically couples the second probe pad of the second die with the first TSV in the first die, wherein the second probe pad of the second die is electrically coupled with the first probe pad of the first die through the conductive interconnect and the first TSV.

2 . The apparatus of claim 1 , wherein the conductive interconnect is formed from a redistribution layer (RDL) and is part of a conductive interconnect structure, through which the second probe pad is electrically coupled with the first probe pad, that includes a die-interface bond pad of the second die, the die-interface bond pad electrically coupled with, and electrically between, the RDL and the first TSV.

3 . The apparatus of claim 1 , wherein:
the first TSV is coupled with a die-interface bond pad, of the first die, that is coupled with a die-interface bond pad of the second die, and the conductive interconnect is electrically coupled with the first TSV through the die-interface bond pad of the second die and the die-interface bond pad of the first die.

4 . The apparatus of claim 3 , further comprising:
a via in contact with the conductive interconnect, and wherein the conductive interconnect is electrically coupled with the die-interface bond pad of the second die through the via.

5 . The apparatus of claim 1 , further comprising:
a second TSV that extends at least partially through the second die, wherein the conductive interconnect is coupled with the second TSV of the second die.

6 . The apparatus of claim 5 , further comprising:
a via in contact with the conductive interconnect and a bond pad of the second TSV, wherein the second probe pad is electrically coupled with the second TSV through the conductive interconnect, the via, and the bond pad of the second TSV.

7 . The apparatus of claim 1 , wherein the second die comprises a second TSV, the apparatus further comprising:
a third die comprising a third probe pad, wherein the second probe pad of the second die is electrically coupled with the third probe pad of the third die through the conductive interconnect and the second TSV.

8 . The apparatus of claim 7 , wherein the third die is wafer-to-wafer hybrid bonded with the second die, die-to-die hybrid bonded with the second die, or die-to-wafer hybrid bonded with the second die.

9 . The apparatus of claim 1 , further comprising:
a third die comprising a third probe pad that is electrically coupled with the first probe pad of the first die through a conductive path that omits the conductive interconnect.

10 . The apparatus of claim 1 , further comprising:
a bond pad, of the first TSV, that is electrically coupled with the first probe pad; and a back-end-of-line (BEOL) portion electrically coupled with, and electrically between, the first TSV and the bond pad of the first TSV.

11 . The apparatus of claim 1 , wherein the first probe pad is configured to convey electrical signals to access circuitry that is coupled with a memory of the first die and the second probe pad is configured to convey electrical signals to access circuitry that is coupled with a memory of the second die.

12 . A method, comprising:
forming a probe pad on surface of a die that includes a first through-silicon-via (TSV) that extends at least partially through the die; forming a first via, within a layer of an oxide material, that is in contact with the probe pad; forming a second via, within the layer of the oxide material, that is in contact with a bond pad of the TSV; and forming a conductive interconnect, within the layer of the oxide material, that is in contact with the first via and the second via and that electrically couples the probe pad with the TSV.

13 . The method of claim 12 , wherein the first via, the second via, and the conductive interconnect are each formed using a dual damascene process.

14 . The method of claim 12 , further comprising:
forming a third via, within a second layer of the oxide material, that is in contact with the conductive interconnect and a die-interface bond pad of the die.

15 . The method of claim 12 , wherein the conductive interconnect is electrically coupled with a die-interface bond pad of the die, the method further comprising:
bonding the die with a second die that includes a second probe pad and a second TSV coupled with a die-interface bond pad of the second die, wherein bonding the die with the second die bonds the die-interface bond pad of the die with the die-interface bond pad of the second die.

16 . The method of claim 15 , wherein bonding the die with the second die comprises bonding using a die-to-wafer hybrid bonding technique, a die-to-die hybrid bonding technique, or a wafer-to-wafer hybrid bonding technique.

17 . The method of claim 15 , further comprising:
probing the die, before bonding the die with the second die, by applying electrical signals to the probe pad of the die; and probing the die, after bonding the die with the second die, by applying electrical signals to the second probe pad of the second die.

18 . The method of claim 12 , further comprising:
bonding the die with a second die that includes a second probe pad, wherein bonding the die with the second die electrically couples the probe pad of the die with the second probe pad of the second die.

19 . The method of claim 18 , wherein:
the conductive interconnect is electrically coupled with a die-interface bond pad of the die through the TSV, and bonding the die with the second die bonds the die-interface bond pad of the die with a die-interface bond pad of the second die.

20 . The method of claim 19 , wherein the second probe pad of the second die is electrically coupled with the probe pad of the die through a second conductive interconnect, of the second die, that electrically couples the second probe pad with a die interface bond of the second die.

21 . The method of claim 19 , further comprising:
forming a third via that is in contact with the conductive interconnect; and forming a die-interface bond pad that is in connect with the third via, wherein the probe pad is electrically coupled with the die-interface bond pad through the conductive interconnect and the third via.

22 . A semiconductor device, comprising:
a first probe pad that is on a physically accessible surface of a stack of semiconductor dies; a second probe pad located at a physically inaccessible surface within the stack of semiconductor dies; and a conductive path that electrically couples the first probe pad with the second probe pad.

23 . The semiconductor device of claim 22 , wherein the stack of semiconductor dies comprises a first die comprising the first probe pad and a second die comprising the second probe pad, the semiconductor device further comprising:
a first die-interface bond pad of the first die; a conductive interconnect, formed from a redistribution layer (RDL), electrically coupled with the second probe pad through a via; and a second die-interface bond pad, of the second die, that electrically couples the conductive interconnect with the first die-interface bond pad.

Assignees

• Micron Technology Inc

Inventors

• Bhushan Bharat
• Parekh Kunal R
• Street Bret K
• Singh Akshay N

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W70/635 Primary

  Through-vias · CPC title