Electroless nickel-electroless palladium-immersion gold (enepig) as a surface finish for embedded die attachments

Patent metadata

Field	Value
Publication number	US-2025218924-A1
Application number	US-202318400878-A
Country	US
Kind code	A1
Filing date	Dec 29, 2023
Priority date	Dec 29, 2023
Publication date	Jul 3, 2025
Grant date	—

Abstract

In embodiments herein, a surface finish (SF) is formed on conductive contacts of a package substrate for connection to an embedded interconnect bridge circuitry die. In some embodiments, the SF may be electroless nickel-electroless palladium-immersion gold (ENEPIG). In other embodiments, the SF may be immersion gold-electroless palladium-immersion gold (IGEPIG). In other embodiments, the SF may include a layer of electrolytic palladium-gold on a layer of indium or on a layer of cobalt-iron.

First claim

1 . An integrated circuit package substrate comprising:
a plurality of metallization layers in dielectric buildup layers; a die within the buildup layers, the die comprising a conductive contact in electrical connection with a conductive contact of a metallization layer; and conductive materials between the conductive contact of the die and the conductive contact of the metallization layer, the conductive materials comprising nickel, phosphorous, tin, and palladium.

2 . The integrated circuit package substrate of claim 1 , wherein the conductive materials comprise an intermetallic compound comprising nickel and phosphorous.

3 . The integrated circuit package substrate of claim 2 , wherein the intermetallic compound comprises phosphorous at between 15-30% by weight.

4 . The integrated circuit package substrate of claim 1 , wherein the conductive materials comprise an intermetallic compound comprising copper, nickel, tin, and palladium.

5 . The integrated circuit package substrate of claim 4 , wherein the intermetallic compound comprises copper at between 20-40% by weight, nickel at between 20-40% by weight, and tin at between 30-50% by weight.

6 . The integrated circuit package substrate of claim 1 , wherein the conductive materials comprise an intermetallic compound comprising nickel, tin, and phosphorous.

7 . The integrated circuit package substrate of claim 1 , wherein the conductive materials comprise a layer on the conductive pads of the metallization layer comprising nickel and phosphorous.

8 . The integrated circuit package substrate of claim 1 , wherein the die is an interconnect bridge circuitry die.

9 . The integrated circuit package substrate of claim 8 , wherein the interconnect bridge circuitry die comprises a through silicon via (TSV) connected to the conductive contact of the die.

10 . The integrated circuit package substrate of claim 1 , wherein the die is encapsulated in a cavity or opening in the buildup layers.

11 . An integrated circuit package comprising:
an integrated circuit package substrate comprising:
a plurality of metallization layers in dielectric buildup layers;
an interconnect bridge circuitry die embedded in the buildup layers, the interconnect bridge circuitry die comprising a via connected between a first conductive contact on a first side of the interconnect bridge circuitry die and a second conductive contact on a second side of the interconnect bridge circuitry die opposite the first side, the second conductive contact in electrical connection with a conductive contact of a metallization layer; and
conductive materials between the second conductive contact of the interconnect bridge circuitry die and the conductive contact of the metallization layer, the conductive materials comprising nickel, phosphorous, tin, and palladium; and
integrated circuit dies coupled to the package substrate, at least two integrated circuit dies interconnected by the interconnect bridge circuitry die.

12 . The integrated circuit package of claim 11 , wherein the conductive materials comprise an intermetallic compound comprising nickel and phosphorous.

13 . The integrated circuit package of claim 12 , wherein the intermetallic compound comprises phosphorous at between 15-30% by weight.

14 . The integrated circuit package of claim 11 , wherein the conductive materials comprise an intermetallic compound comprising copper, nickel, tin, and palladium.

15 . The integrated circuit package of claim 14 , wherein the intermetallic compound comprises copper at between 20-40% by weight, nickel at between 20-40% by weight, and tin at between 30-50% by weight.

16 . The integrated circuit package of claim 11 , wherein the conductive materials comprise an intermetallic compound comprising nickel, tin, and phosphorous.

17 . The integrated circuit package of claim 11 , wherein the second conductive contact of the interconnect bridge circuitry die has a thickness between 5-12 um.

18 . A method of forming an integrated circuit package substrate comprising:
forming buildup layers on a core layer, the buildup layers comprising a plurality of metallization layers; forming a cavity in the buildup layers to expose a subset of conductive contacts of a metallization layer; forming a first surface finish layer on the subset of conductive contacts, the first surface finish layer comprising nickel and having a thickness that is greater than 5 um; forming a second surface finish layer on the first surface finish layer, the second surface finish layer comprising palladium; forming a third surface finish layer on the second surface finish layer, the second surface finish layer comprising gold; placing a die within the cavity such that conductive contacts of the die are in electrical connection with the subset of conductive contacts.

19 . The method of claim 18 , wherein the first surface finish layer is formed using electroless plating, the second surface finish layer is formed using electroless plating, and the third surface finish layer is formed using immersion plating.

20 . The method of claim 18 , wherein the first surface finish layer is between 5-10 um thick, the second surface finish layer is between 0.01-0.10 μm thick, and the third surface finish layer is between 0.01-0.10 μm thick.

Assignees

• Intel Corp

Inventors

• Chatterjee Prithwish
• Sharma Shruti
• Ahmed Numair
• Fang Yuxin
• Jen Wei-Lun
• Alur Narasimha Krishna Siddharth
• Stewart Mollie A
• Pietambaram Srinivas Venkata Ramanuja
• Narute Suresh T

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07255

  changes in materials · CPC title

• H10W72/2528

  Intermetallic compounds · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/072

  of bump connectors · CPC title