Computing device and method of operating the same

Patent metadata

Field	Value
Publication number	US-2025217040-A1
Application number	US-202418935606-A
Country	US
Kind code	A1
Filing date	Nov 3, 2024
Priority date	Dec 27, 2023
Publication date	Jul 3, 2025
Grant date	—

Abstract

A method of operating a computing device according to an aspect of the inventive concept may include accessing a page of a second tier memory, checking a time taken for the access, checking a total number of accesses of the page based on the time taken for the access, and determining whether to terminate promotion of the page to the first tier memory and a timing of the promotion, based on the total number of accesses of the page.

First claim

What is claimed is:

1 . A method of operating a computing device including a first tier memory and a second tier memory, the method comprising:
accessing a page of the second tier memory; checking a time taken for the accessing the page of the second tier memory; checking a total number of accesses of the page based on the time taken for the accessing; and determining whether to terminate a promotion of the page to the first tier memory and a timing of the promotion, based on the total number of accesses of the page, wherein the determining whether to terminate the promotion and the timing of the promotion comprises:
terminating the promotion if the total number of accesses is less than N times, where N is a positive integer;
attempting the promotion at one of a first timing and a second timing if the total number of accesses is equal to or greater than the N times and less than M times, where M is a positive integer greater than N; and attempting the promotion at the first timing if the total number of accesses is equal to or greater than the M times,
wherein a memory capacity of the first tier memory is less than a memory capacity of the second tier memory, and wherein the first timing is temporally earlier than the second timing.

2 . The method of claim 1 , wherein the checking the total number of accesses of the page based on the time taken for the accessing comprises:
checking the total number of accesses if the time taken for the accessing is less than a preset time interval.

3 . The method of claim 2 , wherein the checking the total number of accesses of the page based on the time taken for the accessing comprises:
counting the access if the time taken for the accessing is less than the preset time interval to increase the total number of accesses by 1.

4 . The method of claim 2 , further comprising:
if the time taken for the accessing is equal to or greater than the preset time interval, terminating the attempting for the promotion.

5 . The method of claim 1 , wherein the first timing is before termination of a kernel mode period related to the accessing.

6 . The method of claim 1 ,
wherein the second timing is after termination of a kernel mode period related to the accessing, and wherein demotion is executed after the termination of the kernel mode period.

7 . The method of claim 1 , further comprising:
checking a remaining memory capacity of the first tier memory, wherein the attempting the promotion at the one of the first timing and the second timing if the total number of accesses is equal to or greater than N times and less than M times comprises:
attempting the promotion at the first timing if the first tier memory has the remaining memory capacity; and
attempting the promotion at the second timing if the first tier memory does not have the remaining memory capacity.

8 . The method of claim 1 , further comprising:
checking a remaining memory capacity of the first tier memory, wherein the attempting the promotion at the first timing if the total number of accesses is equal to or greater than M times comprises:
attempting the promotion at the first timing without waiting for demotion if the first tier memory has the remaining memory capacity; and
attempting the promotion at the first timing after waiting for the demotion if the first tier memory does not have the remaining memory capacity.

9 . The method of claim 1 , wherein the N times are 3 times, and the M times are 4 times.

10 . The method of claim 1 , wherein the first tier memory includes dual in-line memory module (DIMM) form factor-based dynamic random access memory (DRAM), and the second tier memory includes compute express link (CXL)-based DRAM.

11 . A computing device comprising:
a first tier memory; a second tier memory, wherein a memory capacity of the second tier memory is greater than a memory capacity of the first tier memory; and a processor, wherein the processor is configured to:
access a page of the second tier memory,
check a time taken for the access,
check a total number of accesses of the page based on the time taken for the access,
identify whether to terminate promotion of the page to the first tier memory and a timing of the promotion, based on the total number of accesses of the page,
terminate the promotion if the total number of accesses is less than N times, where N is a positive integer,
attempt the promotion at one of a first timing and a second timing if the total number of accesses is equal to or greater than the N times and less than M times, where M is a positive integer greater than N, and
attempt the promotion at the first timing if the total number of accesses is equal to or greater than the M times,
wherein the first timing is temporally earlier than the second timing.

12 . The computing device of claim 11 , wherein the processor is further configured to:
check the total number of accesses if the time taken for the access is less than a preset time interval.

13 . The computing device of claim 11 , wherein the processor is further configured to:
count the access if the time taken for the access is less than a preset time interval to increase the total number of accesses by 1.

14 . The computing device of claim 11 , wherein the processor is further configured to:
terminate an attempt for the promotion if the time taken for the access is equal to or greater than a preset time interval.

15 . The computing device of claim 11 , wherein the first timing is before termination of a kernel mode period related to the access.

16 . The computing device of claim 11 ,
wherein the second timing is after termination of a kernel mode period related to the access, and wherein demotion is executed after the termination of the kernel mode period.

17 . The computing device of claim 11 , wherein the processor is further configured to:
check a remaining memory capacity of the first tier memory, attempt the promotion at the first timing if the total number of accesses is equal to or greater than N times and less than M times and the first tier memory has the remaining memory capacity, and attempt the promotion at the second timing if the total number of accesses is equal to or greater than N times and less than M times and the first tier memory does not have the remaining memory capacity.

18 . The computing device of claim 11 , wherein the processor is further configured to:
check a remaining memory capacity of the first tier memory, attempt the promotion at the first timing without waiting for demotion if the total number of accesses is equal to or greater than M times and the first tier memory has the remaining memory capacity, and attempt the promotion at the first timing after waiting for the demotion if the total number of accesses is equal to or greater than M times and the first tier memory does not have the remaining memory capacity.

19 . The computing device of claim 11 , wherein the first tier memory includes dual in-line memory module (DIMM) form factor-based dynamic random access memory (DRAM), and the second tier memory is compute express link (CXL)-based DRAM.

20 . A method of operating a computing device including a first tier memory and a second tier memory, the method comprising:
accessing a page of the second tier memory; checking a time taken for the accessing; checking a total number of accesses of the page based on the time taken for the accessing; updating the total number of accesses of the

Assignees

• Samsung Electronics Co Ltd
• Uif Univ Industry Foundation Yonsei Univ

Inventors

• Kim Minjae
• Ro Won Woo
• Lim Kyeonghoon
• Lee Jiwon

Classifications

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0647

  Migration mechanisms · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/061

  Improving I/O performance · CPC title