Main memory device having heterogeneous memories, computer system including the same, and data management method thereof

Patent metadata

Field	Value
Publication number	US-11379381-B2
Application number	US-201916593756-A
Country	US
Kind code	B2
Filing date	Oct 4, 2019
Priority date	Jan 7, 2019
Publication date	Jul 5, 2022
Grant date	Jul 5, 2022

Abstract

A main memory device includes a first memory device; and a second memory device having an access latency different from that of the first memory device. The first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region.

First claim

What is claimed is:

1. A main memory device comprising:
a first memory device; and
a second memory device having an access latency different from that of the first memory device,
wherein the first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region,
wherein the at least one region includes a plurality of pages,
wherein the first memory device manages the access count for the at least one region rather than each of the plurality of pages,
wherein the first memory device comprises a first memory and a first controller which controls an operation of the first memory,
wherein the first controller comprises:
an access count storage circuit configured with an access count field in which the access count for the at least one region is stored and a hot page address field in which an address of the hot page is stored; and
an access management circuit configured to increment the access count each time the at least one region is accessed, and

wherein, when the access count for the at least one region reaches a threshold value, the access management circuit determines a last accessed page of the at least one region as the hot page, and stores the address of the hot page in the access count storage circuit.

2. The main memory device according to claim 1 , wherein, when a hot data checking command is received from an external device, the first controller checks whether the hot page exists in the first memory, by referring to information stored in the access count storage circuit, and transmits a result of the check to the external device.

3. The main memory device according to claim 2 , wherein the first controller transmits the address of the hot page to the external device as the check result when the hot page exists, and transmits to the external device information indicating that the hot page does not exist as the check result when the hot page does not exist.

4. The main memory device according to claim 3 , wherein, when a data migration command is received from the external device, a data migration operation of exchanging hot data stored in the hot page of the first memory with cold data stored in a second memory of the second memory device is performed.

5. The main memory device according to claim 4 , wherein the first memory comprises a nonvolatile memory, and the second memory comprises a volatile memory.

6. The main memory device according to claim 5 , wherein the nonvolatile memory comprises a phase change random access memory (PCRAM), and the volatile memory comprises a dynamic random access memory (DRAM).

7. The main memory device according to claim 1 , wherein an access latency of the first memory device is longer than the access latency of the second memory device.

8. A main memory device comprising:
a first memory device; and
a second memory device having a power consumption per unit time different from that of the first memory device,
wherein the first memory device determines, based on an access count for at least one region of the first memory device, a hot page included in the at least one region,
wherein the at least one region includes a plurality of pages,
wherein the first memory device manages the access count for the at least one region rather than each of the plurality of pages, and
wherein the first memory device comprises a first memory and a first controller which controls an operation of the first memory,
wherein the first controller comprises:
an access count storage circuit configured with an access count field in which the access count for the at least one region is stored and a hot page address field in which an address of the hot page is stored; and
an access management circuit configured to increment the access count each time the at least one region is accessed, and

wherein, when the access count for the at least one region reaches a threshold value, the access management circuit determines a last accessed page of the at least one region as the hot page, and stores the address of the hot page in the access count storage circuit.

9. The main memory device according to claim 8 , wherein a power consumption per unit time of the first memory device is larger than the power consumption per unit time of the second memory device.

10. A computer system comprising:
a central processing unit (CPU); and
a main memory device coupled with the CPU through a system bus,
wherein the main memory device comprises:
a first memory device; and
a second memory device having an access latency shorter than that of the first memory device, and
wherein the first memory device determines, based on an access count for each of one or more regions of the first memory device, a hot page included in at least one of the one or more regions,
wherein the each of the one or more regions include a plurality of pages,
wherein the first memory device manages the access count for the each of the one or more regions rather than each of the plurality of pages,
wherein the first memory device comprises a first memory and a first controller which controls an operation of the first memory, and
wherein the first controller comprises:
an access count storage circuit configured with an access count field in which the access count for each of the one or more regions are stored and a hot page address field in which an address of the hot page is stored; and
an access management circuit configured to increment, each time each of the one or more regions is accessed, the access count corresponding to the region accessed, and

wherein, when an access count of a region of the one or more regions reaches a threshold value, the access management circuit determines a last accessed page in the corresponding region as the hot page, and stores an address corresponding to the determined hot page in the access count storage circuit, as the address of the hot page.

11. The computer system according to claim 10 , wherein the CPU manages a first least recently used (LRU) queue configured to store page addresses accessed in the first memory in access order, and a second LRU queue configured to store page addresses accessed in a second memory of the second memory device in access order.

12. The computer system according to claim 11 , wherein the CPU transmits to the first memory device at each of multiple set times a hot data checking command for performing a hot page checking operation.

13. The computer system according to claim 12 , wherein the first memory device checks whether the hot page exists in the first memory, by referring to the hot page address field of the access count storage circuit, in response to the hot data checking command received from the CPU, and transmits a result of the check to the CPU.

14. The computer system according to claim 13 , wherein the first memory device transmits the address corresponding to the hot page to the CPU as the check result when the hot page exists, and transmits to the CPU information indicating that the hot data does not exist as the check result when the hot page does not exist.

15. The computer system according to claim 14 , wherein the CPU determines a cold page in the second memory by referring to the second LRU queue, and transmits a data migration command to the main memory device for exchanging hot data stored in the hot page of the first memory and cold data stored in the cold page of the second memory.

16. The computer system according to claim 15 , wherein, according to the data migration command received from the CPU, the second memory device r

Assignees

• Sk Hynix Inc

Inventors

• Han Mi Seon
• Mun Yun Jeong
• Joo Young Pyo

Classifications

• G06F3/0631

  by allocating resources to storage systems · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F12/123

  with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list · CPC title

• G06F3/0647 Primary

  Migration mechanisms · CPC title

• G06F12/1458

  by checking the subject access rights · CPC title