Level-based fault detection for a row driver of an optical sensor

Patent metadata

Field	Value
Publication number	US-2025216252-A1
Application number	US-202318400359-A
Country	US
Kind code	A1
Filing date	Dec 29, 2023
Priority date	Dec 29, 2023
Publication date	Jul 3, 2025
Grant date	—

Abstract

An illustrative fault detection system may include an input node, a transport circuit, and a comparison circuit. The input node may electrically connect to a row driver that produces, on the input node, a row driver voltage having one of a plurality of analog voltage levels. The transport circuit may be configured to transport, when the row driver is selected from a plurality of row drivers, the row driver voltage to a monitoring node shared by a plurality of fault detection systems including the fault detection system. The comparison circuit may be shared by the plurality of fault detection systems and may be configured to generate a digital output by conditioning a voltage from the monitoring node, performing a comparison between the conditioned voltage and a reference voltage, and latching the digital output based on the comparison. Corresponding systems, integrated circuits, and methods are also disclosed.

First claim

What is claimed is:

1 . A fault detection system comprising:
an input node electrically connected to a row driver that produces, on the input node, a row driver voltage having one of a plurality of analog voltage levels; a transport circuit configured to transport, when the row driver is selected from a plurality of row drivers, the row driver voltage to a monitoring node shared by a plurality of fault detection systems including the fault detection system; and a comparison circuit shared by the plurality of fault detection systems and configured to generate a digital output based on the row driver voltage and a reference voltage.

2 . The fault detection system of claim 1 , wherein the row driver is configured to activate a plurality of transistors one at a time so that the row driver voltage is driven at:
a first voltage level of the plurality of analog voltage levels when a first PMOS transistor of the plurality of transistors is activated; a second voltage level of the plurality of analog voltage levels when a second PMOS transistor of the plurality of transistors is activated; a third voltage level of the plurality of analog voltage levels when a first NMOS transistor of the plurality of transistors is activated; and a fourth voltage level of the plurality of analog voltage levels when a second NMOS transistor of the plurality of transistors is activated.

3 . The fault detection system of claim 2 , wherein the digital output includes:
a first output bit determined at a first time when the reference voltage has a first reference level, the first output bit indicating whether a defect is detected in the first NMOS transistor or the second NMOS transistor; and a second output bit determined at a second time when the reference voltage has a second reference level, the second output bit indicating whether a defect is detected in the first PMOS transistor or the second PMOS transistor.

4 . The fault detection system of claim 3 , wherein the comparison circuit includes a storage circuit configured to store and output the first output bit and the second output bit of the digital output.

5 . The fault detection system of claim 1 , wherein the transport circuit includes a first routing transistor and a second routing transistor collectively configured to route the row driver voltage to the monitoring node either:
by way of a first path through the first routing transistor when an analog voltage level of the row driver voltage is greater than a threshold level, or by way of a second path through the second routing transistor when the analog voltage level of the row driver voltage is less than the threshold level.

6 . The fault detection system of claim 5 , wherein the transport circuit further includes:
a first shield transistor configured to protect the first routing transistor from voltage levels outside a first operating range of the first routing transistor; and a second shield transistor configured to protect the second routing transistor from voltage levels outside a second operating range of the second routing transistor.

7 . The fault detection system of claim 1 , wherein the transport circuit includes:
a first monitor selection transistor that, when activated, connects the monitoring node to a first path by way of which the row driver voltage is routed when an analog voltage level of the row driver voltage is greater than a threshold level; a second monitor selection transistor that, when activated, connects the monitoring node to a second path by way of which the row driver voltage is routed when the analog voltage level of the row driver voltage is less than the threshold level; and a control node on which a control signal is received, the control signal being configured to control activation of the first monitor selection transistor and the second monitor selection transistor.

8 . The fault detection system of claim 7 , wherein the control signal is configured to control activation of the first monitor selection transistor and the second monitor selection transistor in accordance with a pre-charge phase and an evaluation phase of a period when the row driver is selected from the plurality of row drivers.

9 . The fault detection system of claim 7 , wherein the control signal is configured to control activation of the first monitor selection transistor and the second monitor selection transistor in accordance with a protection period when a different row driver other than the row driver is selected from the plurality of row drivers.

10 . The fault detection system of claim 1 , wherein the comparison circuit includes:
a first capacitor electrically connected to the monitoring node; a second capacitor electrically connected between the first capacitor and ground; a conditioned monitoring node between the first capacitor and the second capacitor; a comparator device connected to the conditioned monitoring node and a reference node for the reference voltage; a first reference control transistor that, when activated, connects a first scaling reference node to the monitoring node; and a second reference control transistor that, when activated, connects a second scaling reference node to the conditioned monitoring node.

11 . The fault detection system of claim 10 , wherein the comparison circuit further includes a storage circuit connected to an output of the comparator device and configured to:
latch the digital output based on an enable signal; and store and output the digital output.

12 . An optical sensor integrated circuit comprising:
a plurality of row drivers including a row driver configured to produce a row driver voltage; and a plurality of fault detection systems for the plurality of row drivers, the plurality of fault detection systems including a fault detection system for the row driver, the fault detection system including:
an input node electrically connected to the row driver to receive the row driver voltage,
a monitoring node shared by the plurality of fault detection systems,
a transport circuit configured to receive the row driver voltage from the input node and transport the row driver voltage to the monitoring node when the row driver is selected from the plurality of row drivers, and
a comparison circuit shared by the plurality of fault detection systems, the comparison circuit being configured to receive the row driver voltage via the monitoring node and to generate a digital output based on the row driver voltage and a reference voltage.

13 . The optical sensor integrated circuit of claim 12 , wherein the row driver is configured to activate a plurality of transistors one at a time so that the row driver voltage is driven at:
a first voltage level when a first PMOS transistor of the plurality of transistors is activated; a second voltage level when a second PMOS transistor of the plurality of transistors is activated; a third voltage level when a first NMOS transistor of the plurality of transistors is activated; and a fourth voltage level when a second NMOS transistor of the plurality of transistors is activated; wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are all different transistors of the plurality of transistors.

14 . The optical sensor integrated circuit of claim 13 , wherein the digital output includes:
a first output bit determined at a first time when the reference voltage has a first reference level, the first output bit indicating whether a defect is detected in the first NMOS transistor or the second NMOS transistor; and a second output bit determi

Assignees

• Semiconductor Components Ind Llc

Inventors

• Gurindagunta Sundaraiah
• Kuruba Revathi

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G01R31/2851 Primary

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

• H04N17/002

  for television cameras · CPC title

• G01J1/44 Primary

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title