Method of manufacturing mram device with enhanced etch control

Patent metadata

Field	Value
Publication number	US-2025212694-A1
Application number	US-202519076941-A
Country	US
Kind code	A1
Filing date	Mar 11, 2025
Priority date	Apr 22, 2020
Publication date	Jun 26, 2025
Grant date	—

Abstract

A method of manufacturing a semiconductor device includes: providing a substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; depositing a first conductive layer over the MTJ layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the MTJ layer in the memory region; and etching the patterned second conductive layer and the MTJ layer to form a top electrode and an MTJ, respectively, in the memory region.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
depositing a magnetic tunnel junction layer over a memory region and a logic region of a substrate; depositing a sacrificial layer over the magnetic tunnel junction layer; etching and removing the sacrificial layer in the memory region to expose the magnetic tunnel junction layer in the memory region, while keeping the magnetic tunnel junction layer in the logic region covered; depositing a first conductive layer in the memory region and the logic region after etching the sacrificial layer such that the first conductive layer is in contact with the magnetic tunnel junction layer in the memory region and the sacrificial layer separates the magnetic tunnel junction layer from the first conductive layer in the logic region; and patterning the first conductive layer in the memory region to form a patterned first conductive layer and removing the first conductive layer in the logic region.

2 . The method of claim 1 , further comprising:
depositing a bottom electrode layer across the logic region and the memory region before depositing the magnetic tunnel junction layer; and depositing the magnetic tunnel junction layer over the bottom electrode layer.

3 . The method of claim 2 , further comprising:
patterning the magnetic tunnel junction layer and the bottom electrode layer using the patterned first conductive layer as an etching mask to form a magnetic tunnel junction cell structure in the memory region.

4 . The method of claim 3 , further comprising, prior to depositing of the bottom electrode layer:
forming a metal line layer having a metal line; depositing a first dielectric layer in the memory region and the logic region over the metal line layer; and forming a bottom electrode via within the first dielectric layer in the memory region.

5 . The method of claim 4 , wherein during patterning of the magnetic tunnel junction layer and the bottom electrode layer in the memory region, a thickness of the first conductive layer is reduced.

6 . The method of claim 5 , wherein the metal line is covered by the first dielectric layer in the logic region upon completion of patterning the magnetic tunnel junction layer and the bottom electrode layer.

7 . The method of claim 3 , wherein patterning the first conductive layer in the memory region further comprises:
depositing a mask layer over the first conductive layer; patterning the mask layer to form a patterned mask layer; and patterning the first conductive layer using the patterned mask layer as an etch mask.

8 . The method of claim 7 , wherein the mask layer comprises a same material as a material in the sacrificial layer.

9 . The method of claim 7 , wherein patterning the magnetic tunnel junction layer and the bottom electrode layer in the memory region comprises performing an ion bombardment etching to remove an entirety of the mask layer and a portion of the first conductive layer in the memory region.

10 . The method of claim 9 , wherein the ion bombardment etching etches the magnetic tunnel junction layer using at least the first conductive layer as an etch mask to form a magnetic tunnel junction structure in the memory region.

11 . The method of claim 10 , wherein the ion bombardment etching further etches the bottom electrode layer using the first conductive layer as the etch mask to form a cell bottom electrode.

12 . The method of claim 9 , wherein the ion bombardment etching removes the mask layer and the first conductive layer in the logic region.

13 . A method of manufacturing a semiconductor device, comprising:
depositing a bottom electrode layer and a magnetic tunnel junction layer over a memory region and a logic region of a substrate; depositing an etch buffer layer over the magnetic tunnel junction layer; etching and removing the etch buffer layer in the memory region to expose the magnetic tunnel junction layer in the memory region, while keeping the magnetic tunnel junction layer in the logic region covered; and depositing a first conductive layer over the magnetic tunnel junction layer in the memory region and over the etch buffer layer in the logic region after etching the etch buffer layer such that the first conductive layer is in contact with the magnetic tunnel junction layer in the memory region and the etch buffer layer separates the magnetic tunnel junction layer from the first conductive layer in the logic region, wherein the first conductive layer as deposited is thicker than the bottom electrode layer.

14 . The method of claim 13 , further comprising:
depositing a mask layer over the first conductive layer; patterning the mask layer to form a pattern of a top electrode in the memory region; patterning the first conductive layer by transferring the pattern to the first conductive layer in the memory region to form a patterned first conductive layer; and etching the mask layer, the patterned first conductive layer, the magnetic tunnel junction layer, and the bottom electrode layer using an etching operation to form the top electrode, a magnetic tunnel junction and a bottom electrode in the memory region.

15 . The method of claim 14 , wherein patterning the first conductive layer comprises removing the first conductive layer in the logic region.

16 . The method of claim 14 , wherein the first conductive layer as deposited is thicker than the bottom electrode layer.

17 . The method of claim 14 , wherein the etch buffer layer is made of a dielectric material.

18 . A method of manufacturing a semiconductor device, comprising:
forming a metal line layer having a metal line in a memory region of a substrate comprising the memory region and a logic region; depositing a first dielectric layer in the memory region and the logic region over the metal line layer; forming a bottom electrode via within the first dielectric layer in the memory region; depositing a bottom electrode layer and a magnetic tunnel junction layer over the memory region and the logic region of the substrate; depositing and etching an etch buffer layer so that the etch buffer layer is formed only over the magnetic tunnel junction layer in the logic region; and depositing a first conductive layer over the magnetic tunnel junction layer in the memory region and over the etch buffer layer in the logic region such that the first conductive layer is in contact with the magnetic tunnel junction layer in the memory region and the etch buffer layer separates the magnetic tunnel junction layer from the first conductive layer in the logic region.

19 . The method of claim 18 , further comprising:
etching the first conductive layer to expose the magnetic tunnel junction layer in the memory region; and etching the first conductive layer, the magnetic tunnel junction layer, and the bottom electrode layer to obtain a magnetoresistive random access memory structure including a bottom electrode, a magnetic tunnel junction, and a top electrode having a trapezoid shape, wherein a longer parallel side of the trapezoid shape is the bottom electrode and a shorter parallel side of the trapezoid shape is the top electrode.

20 . The method of claim 19 , further comprising forming a spacer laterally surrounding sidewalls of the top electrode, the magnetic tunnel junction, and the bottom electrode.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chien Yu-Jen
• Wu Jung-Tang
• Wu Szu-Hua
• Lee Chin-Szu
• Wu Meng-Yu

Classifications

• H10N50/80

  Constructional details · CPC title

• H10B61/22 Primary

  of the field-effect transistor [FET] type · CPC title

• H10N50/85

  Materials of the active region · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title