Inner spacer structure and methods of forming such

Patent metadata

Field	Value
Publication number	US-2025212498-A1
Application number	US-202519081826-A
Country	US
Kind code	A1
Filing date	Mar 17, 2025
Priority date	Apr 28, 2021
Publication date	Jun 26, 2025
Grant date	—

Abstract

A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first stack of semiconductor layers and a second stack of semiconductor layers over a substrate; a source/drain feature disposed between the first stack of semiconductor layers and the second stack of semiconductor layers along a direction; a gate structure wrapping around each of the second stack of semiconductor layers; a first gate spacer disposed over a topmost one of the first stack of semiconductor layers; a second gate spacer disposed over a topmost one of the second stack of semiconductor layers and along a sidewall of the gate structure; and a contact etch stop layer (CESL) extending continuously from over a top surface of the first gate spacer to along a sidewall of the second gate spacer, wherein the first stack of semiconductor layers are interleaved by a plurality of inner spacer features, wherein one of the plurality of inner spacer features includes a lateral dimension along the direction, wherein the lateral dimension varies along a vertical direction perpendicular to the direction.

2 . The semiconductor device of claim 1 , further comprising:
a substrate; and a base fin over the substrate, wherein the first stack of semiconductor layers and the second stack of semiconductor layers are disposed over the base fin.

3 . The semiconductor device of claim 2 , further comprising:
an isolation feature disposed over the substrate and interfacing sidewalls of the base fin.

4 . The semiconductor device of claim 1 , wherein the first gate spacer and the second gate spacer comprise silicon nitride, silicon oxide, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, carbon doped oxide, nitrogen doped oxide, porous oxide, or a combination thereof.

5 . The semiconductor device of claim 1 , wherein the source/drain feature interfaces the plurality of inner spacer features.

6 . The semiconductor device of claim 1 , wherein the second gate spacer comprises:
a first layer interfacing the gate structure and a top surface of the topmost one of the second stack of semiconductor layers; and a second layer spaced apart from the gate structure and the top surface of the topmost one of the second stack of semiconductor layers by the first layer.

7 . The semiconductor device of claim 1 , wherein a portion of the source/drain feature extends between two of the first stack of semiconductor layers.

8 . The semiconductor device of claim 1 ,
wherein the lateral dimension comprises a first width at an interface between one of the first stack of semiconductor layers and the one of the plurality of inner spacer features, and a second width at a half-height level of the one of the plurality of inner spacer features, and wherein a ratio of the first width to the second width is about 0.65 to about 1.

9 . A semiconductor structure, comprising:
a substrate; a base fin over the substrate; a plurality of channel layers disposed over the base fin; a source/drain feature interfacing the plurality of channel layers and partially extending into the base fin; a gate structure wrapping around each of the plurality of channel layers; a gate spacer disposed over a topmost one of the plurality of channel layers; a contact etch stop layer (CESL) extending continuously from over a top surface of the source/drain feature to over a top surface of the gate spacer; and a plurality of inner spacer features interleaving the plurality of channel layers, wherein one of the plurality of the inner spacer features comprise a curved surface interfacing the gate structure.

10 . The semiconductor structure of claim 9 , wherein the top surface of the source/drain feature is higher than a top surface of the gate spacer.

11 . The semiconductor structure of claim 9 , wherein a portion of the source/drain feature extends between two of the plurality of channel layers.

12 . The semiconductor structure of claim 9 , wherein the source/drain feature interfaces the plurality of inner spacer features.

13 . The semiconductor structure of claim 9 ,
wherein the gate structure comprises a gate dielectric layer and a conductive metal layer over the gate dielectric layer, wherein a dielectric constant of the gate dielectric layer is between about 18 and about 40.

14 . The semiconductor structure of claim 9 , wherein the gate spacer comprises:
a first layer interfacing a top surface of the topmost one of the plurality of channel layers; and a second layer spaced apart from the top surface of the topmost one of the plurality of channel layers by the first layer.

15 . The semiconductor structure of claim 14 , wherein the first layer and the second layer comprise silicon nitride, silicon oxide, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, carbon doped oxide, nitrogen doped oxide, porous oxide, or a combination thereof.

16 . A semiconductor structure, comprising:
a substrate; a base fin over the substrate; a plurality of channel layers disposed over the base fin and extending along a direction; a source/drain feature interfacing the plurality of channel layers and partially extending into the base fin; a gate structure wrapping around each of the plurality of channel layers; a gate spacer disposed over a topmost one of the plurality of channel layers; a contact etch stop layer (CESL) extending continuously from over a top surface of the source/drain feature to over a top surface of the gate spacer; and a plurality of inner spacer features interleaving the plurality of channel layers, wherein one of the plurality of inner spacer features interfaces two of the plurality of channel layers at an interface, wherein a tangential direction of a sidewall surface of the one of the plurality of inner spacer features forms an angle with the direction, wherein the angle is between about 30° and about 90°.

17 . The semiconductor structure of claim 16 , wherein the sidewall surface is curved.

18 . The semiconductor structure of claim 16 , wherein the source/drain feature interfaces the plurality of inner spacer features.

19 . The semiconductor structure of claim 16 , wherein the top surface of the source/drain feature is higher than a top surface of the gate spacer.

20 . The semiconductor structure of claim 16 , wherein a portion of the source/drain feature extends between two of the plurality of channel layers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Che-Lun
• Kuo Jiun-Ming
• Tsai Ji-Yin
• Peng Yuan-Ching

Classifications

• H10P50/642 Primary

  Chemical etching · CPC title

• H10P14/3452

  Microstructure · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title