Methods and apparatus to monitor power transistors

Patent metadata

Field	Value
Publication number	US-2025211222-A1
Application number	US-202418427427-A
Country	US
Kind code	A1
Filing date	Jan 30, 2024
Priority date	Dec 20, 2023
Publication date	Jun 26, 2025
Grant date	—

Abstract

An example apparatus includes: a first transistor implemented using Gallium Nitride (GaN), the first transistor having: a drain configured to receive an input voltage from a power supply; a gate configured to receive a voltage from control circuitry; and a source; a second transistor implemented using GaN, the second transistor having: a drain coupled to the source of the first transistor; a gate coupled to a current source; and a source configured to provide an output voltage based on a voltage at the source of the first transistor; and a third transistor implemented using GaN, the third transistor having: a drain coupled to the source of the first transistor and the drain of the second transistor; a gate; and a source configured to be coupled to ground.

First claim

1 . An apparatus comprising:
a first transistor implemented using Gallium Nitride (GaN), the first transistor having:
a drain configured to receive an input voltage from a power supply;
a gate configured to receive a voltage from control circuitry; and
a source;
a second transistor implemented using GaN, the second transistor having:
a drain coupled to the source of the first transistor;
a gate coupled to a current source; and
a source configured to provide an output voltage based on a voltage at the source of the first transistor; and
a third transistor implemented using GaN, the third transistor having:
a drain coupled to the source of the first transistor and the drain of the second transistor;
a gate; and
a source configured to be coupled to ground.

2 . The apparatus of claim 1 , wherein the output voltage is used by the control circuitry to detect if the third transistor has crossed a short circuit desaturation threshold.

3 . The apparatus of claim 1 , wherein: the output voltage is used by the control circuitry to detect if a voltage at the drain of the third transistor crosses below zero volts.

4 . The apparatus of claim 21 , wherein the device includes:
a fourth transistor having:
a drain coupled to the source of the second transistor;
a gate coupled to the source of the second transistor;
a source coupled to the current source and the gate of the second transistor;
a fifth transistor having:
a drain coupled to the current source and the gate of the second transistor;
a gate coupled to the current source and the gate of the second transistor; and
a source; and
a sixth transistor having:
a drain coupled to the source of the fifth transistor;
a gate coupled to the source of the fifth transistor; and
a source coupled to the source of the second transistor, the drain of the fourth transistor and the gate of the fourth transistor.

5 . The apparatus of claim 4 , wherein the fourth transistor, the fifth transistor, and the sixth transistor are implemented using GaN.

6 . The apparatus of claim 4 , wherein:
the fifth transistor and the sixth transistor are configured to prevent positive bias between the gate and the source of the second transistor; and the fourth transistor is configured to prevent negative between the gate and the source of the second transistor.

7 . The apparatus of claim 4 , wherein:
a voltage at the drain of the third transistor is a drain voltage; and in response to the drain voltage being below a voltage threshold:
the apparatus is configured to keep the second transistor powered on; and
the second transistor is configured to generate an output voltage that is proportional to the drain voltage.

8 . The apparatus of claim 7 , wherein:
the control circuitry is implemented in a Silicon die; and the apparatus is configured to block, in response to the drain voltage being above a voltage threshold, the output voltage from being proportional to the drain voltage to protect the Silicon die from receiving a voltage that may damage the control circuitry.

9 . The apparatus of claim 8 , wherein to block the output voltage from being proportional to the drain voltage, the apparatus is configured to turn the second transistor off in response to the drain voltage being greater than a voltage threshold.

10 . A system comprising:
control circuitry configured to produce a first control voltage and a second control voltage; a first transistor having:
a drain configured to receive an input voltage from a power supply;
a gate configured to receive the first control voltage; and
a source;
a current source configured to produce a current based on a reference voltage; a second transistor having:
a drain coupled to the source of the first transistor;
a gate coupled to the current source; and
a source configured to provide an output voltage based on a voltage at the source of the first transistor; and
a third transistor having:
a drain coupled to the source of the first transistor and the drain of the second transistor;
a gate; and
a source configured to be coupled to ground.

11 . The system of claim 10 , wherein:
the control circuitry and the current source are implemented using Silicon; and the first transistor, the second transistor, and the third transistor are implemented using Gallium Nitride.

12 . The system of claim 10 , wherein:
a voltage at the drain of the third transistor is a drain voltage; and in response to drain voltage being below a voltage threshold:
the current source is configured to keep the second transistor powered on by providing current to the source of the second transistor; and
the second transistor is configured to generate an output voltage that is proportional to the drain voltage.

13 . (canceled)

14 . The system of claim 10 , wherein:
the system further includes a charge pump configured to receive a reference voltage and coupled to the current source; and the current source is to produce the current using an output of the charge pump.

15 . The system of claim 10 , further including voltage divider circuitry that includes:
a first resistor having:
a first terminal coupled to the source of the second transistor; and
a second terminal;
a fourth transistor having:
a drain coupled to the second terminal of the first resistor;
a gate configured to receive a reference voltage; and
a source;
a diode having:
a positive terminal coupled to the source of the fourth transistor; and
a negative terminal configured to receive a reference voltage;
a second resistor having:
a first terminal coupled to the source of the fourth transistor; and
a second terminal; and
a fifth transistor having:
a drain coupled to the second terminal of the second resistor;
a gate coupled to the gate of the third transistor; and
a second current configured to be coupled to ground.

16 . The system of claim 15 , wherein in response to the third transistor being powered on:
the control circuitry is configured to provide the second control voltage such that the voltage divider circuitry is enabled; the source of the fourth transistor is coupled to the control circuitry; the voltage at the source of the fourth transistor is less than a voltage at the drain of the third transistor; and the control circuitry is configured to use the voltage at the source of the fourth transistor to detect if third transistor have crossed a short circuit desaturation threshold.

17 . The system of claim 15 , wherein:
a voltage at the drain of the third transistor is a drain voltage; in response to the third transistor being powered off: the control circuitry is configured to provide the second control voltage such that the voltage divider circuitry is disabled; the source of the fourth transistor is coupled to the control circuitry; the voltage at the source of the fourth transistor matches the drain voltage; and the control circuitry is configured to use the voltage at the source of the fourth transistor to detect if the drain voltage crosses zero volts.

18 . (canceled)

19 . A non-transitory computer-readable storage medium comprising instructions to cause programmable circuitry on a first integrated circuit die to at least:
receive an input voltage at a sense transistor that is integrated between a high-side transistor and a low-side transistor, the sense transistor, high-side transistor, and low-side transistor implemented on second and third integrated circuit dies that are separate from the

Assignees

• Texas Instruments Inc

Inventors

• Yan Dong
• Xie Yong
• Schemm Nathan Richard
• Kaya Cetin
• Kaufmann Maik Peter
• Herzer Stefan

Classifications

• G01R31/2637

  for testing other individual devices (G01R31/2608 - G01R31/2632, G01R31/27 take precedence) · CPC title

• G01R31/2607

  Circuits therefor (G01R31/2642 takes precedence) · CPC title

• G01R31/2601 Primary

  Apparatus or methods therefor (G01R31/2607, G01R31/2642 take precedence) · CPC title

• H02M1/0051

  Diode reverse recovery losses · CPC title

• H02M1/0058

  by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero (using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826) · CPC title