Electronic device

Patent metadata

Field	Value
Publication number	US-2024136424-A1
Application number	US-202318485194-A
Country	US
Kind code	A1
Filing date	Oct 11, 2023
Priority date	Oct 17, 2022
Publication date	Apr 25, 2024
Grant date	—

Abstract

The present disclosure concerns a driver of a first e-mode type HEMT power transistor adapted to receiving a maximum voltage of 650 V between its drain and its source, the circuit being formed inside and on top of a monolithic semiconductor substrate having a surface covered with a gallium nitride layer, and comprising at least a second e-mode type transistor adapted to directly transmitting a control voltage to the gate of the first transistor and having an area greater than 5 mm 2 .

First claim

1 . A device, comprising:
a monolithic semiconductor substrate; a gallium nitride layer on the substrate; a first e-mode type HEMT power transistor configured to receive a maximum voltage of 650 V between a drain and a source; a driver of the first e-mode type HEMT power transistor; a circuit inside and on top of the monolithic semiconductor substrate, the circuit including: at least a second e-mode type transistor configured to directly transmit a control voltage to a gate of the first transistor, the second transistor having an area greater than 5 mm 2 .

2 . The circuit according to claim 1 , wherein the second transistor has an area in the range from 10 to 15 mm 2 .

3 . The circuit according to claim 1 , wherein the second transistor is formed of an assembly of a plurality of e-mode type transistors.

4 . A device, comprising:
a substrate; a gallium nitride layer on the substrate; a first e-mode type HEMT power transistor in the gallium nitride layer, the first power transistor including a first terminal, a second terminal, and a third terminal; a driver coupled to the first power transistor, the driver including: a second transistor coupled to the first terminal and second terminal of the first power transistor; a third transistor coupled to the second terminal and to VDD; and a triggering circuit coupled to the third transistor.

5 . The device of claim 4 wherein the driver includes a fourth transistor coupled between the first terminal and the triggering circuit.

6 . The device of claim 5 wherein the driver includes a fifth transistor coupled between a gate of the fourth transistor and the first terminal.

7 . The device of claim 6 wherein the driver includes a voltage regulation circuit coupled to the fifth transistor.

8 . The device of claim 7 wherein the driver includes an inverter coupled to a gate of the fifth transistor.

9 . A device, comprising:
a gallium nitride layer; a first power transistor in the gallium nitride layer, the first power transistor being an emission mode type of high electron mobility transistor (HEMT); a driver coupled to the first power transistor, the driver including:
a second transistor coupled to the first power transistor;
a third transistor coupled to the second transistor and the first power transistor;
a fourth transistor coupled to the third transistor;
a triggering circuit coupled to the third and fourth transistor;
a voltage regulation circuit coupled to the fourth transistor.

10 . The device of claim 9 wherein the driver includes a first resistor and a fifth transistor coupled to the fourth transistor and the voltage regulation circuit.

11 . The device of claim 10 wherein the driver includes a sixth transistor coupled to the first resistor and the voltage regulation circuit.

12 . The device of claim 11 wherein the driver includes an inverter coupled between the sixth transistor and the fifth transistor.

13 . The device of claim 12 wherein the driver includes a logic circuit coupled to the inverter and the voltage regulation circuit.

14 . The device of claim 13 wherein sixth transistor is coupled in parallel with the first resistor.

15 . The device of claim 14 wherein a gate of the sixth transistor is coupled to an input of the inverter and an output of the inverter is coupled to a gate of the fifth transistor.

16 . The device of claim 15 wherein a gate of the first power transistor is coupled to a node between the second and third transistors.

17 . The device of claim 16 wherein a gate of the fourth transistor is coupled to the first resistor.

Assignees

• St Microelectronics Rousset

Inventors

• Bourguine Loic

Classifications

• H10D84/0123

  Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs · CPC title

• H10D30/477

  Vertical HEMTs or vertical HHMTs · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D84/05

  using Group III-V technology · CPC title

• H10D30/475

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title