Power converter having improved zero current detecting feature

Patent metadata

Field	Value
Publication number	US-2025211087-A1
Application number	US-202318396741-A
Country	US
Kind code	A1
Filing date	Dec 27, 2023
Priority date	Dec 21, 2023
Publication date	Jun 26, 2025
Grant date	—

Abstract

Technology regarded to an electric circuit, particularly a zero current detection circuit, is disclosed. The proposed zero current detection circuit has a calibration circuit that calibrates an offset error thereof. The offset calibration circuit detects a delay between an output time point of the zero current detection circuit and a moment of change in voltage of the common node and outputs a calibration signal accordingly. The zero current detection circuit includes a pre-amplifier that calibrates a differential voltage according to an offset control signal and a phase comparator that detects a zero current point from the differential voltage.

First claim

What is claimed is:

1 . A power converter comprising:
an energy storage element; a low-voltage side power switch having one end connected to a common node VX and configured to switch charging of the energy storage element with input power; a high-voltage side power switch having one end connected to the common node and configured to switch discharging of power stored in the energy storage element to a load; a switching controller configured to generate and output switching control signals for controlling on and off states of the high-voltage side power switch and the low-voltage side power switch; and a zero current detection circuit configured to compare outputs of the common node VX and a reference node VR, detect a zero current moment, and output a detection signal to the switching controller, wherein the power converter further comprises an offset calibrator configured to detect an error between an output time point of the zero current detection circuit and a falling time of common node output and to output a corresponding calibration signal to the zero current detection circuit.

2 . The power converter according to claim 1 , wherein the offset calibrator comprises a phase detector configured to receive an output signal of the zero current detection circuit and a falling time signal of the common node output to detect an error.

3 . The power converter according to claim 1 , wherein the offset calibrator comprises:
a falling time detector configured to detect the falling time of the common node output; a phase detector configured to detect an error between output of the zero current detection circuit and output of the falling time detector; and an offset signal generator configured to output an offset control signal proportional to the detected error.

4 . The power converter according to claim 3 , wherein the zero current detection circuit comprises:
a pre-amplifier configured to differentially amplify voltages of the common node and the reference node and adjust a differential voltage according to the offset control signal; and a phase comparator configured to receive the differential voltage and detect a zero current point.

5 . The power converter according to claim 3 , wherein the offset signal generator comprises:
a duration detector configured to detect duration of a phase difference signal output by the phase detector; and a counter configured to output an offset control signal increasing in the duration detected by the duration detector.

6 . The power converter according to claim 5 , wherein the zero current detection circuit comprises:
a pre-amplifier configured to differentially amplify voltages of the common node and the reference node and adjust a differential voltage according to the offset control signal; and a phase comparator configured to receive the differential voltage and detect a zero current point.

7 . The power converter according to claim 6 , wherein the pre-amplifier comprises:
a first differential amplifier configured to differentially amplify the voltages of the common node and the reference node and output a positive differential voltage; a second differential amplifier configured to differentially amplify the voltages of the common node and the reference node and output a negative differential voltage; and a common current adjuster configured to adjust a common current of any one of the first or second differential amplifier according to the offset control signal.

8 . The power converter according to claim 7 , wherein the common current adjuster comprises an array resistor connected between any one common terminal of the first or second differential amplifier and a power terminal, connection of each corresponding resistor being switched by each bit of counter output.

9 . The power converter according to claim 1 , wherein the power converter is a boost type power converter, and the reference node is an output node.

10 . The power converter according to claim 3 , wherein the zero current detection circuit comprises:
a comparison circuit including a plurality of dynamic comparators each including a pre-amplifier configured to differentially amplify voltages of the common node and the reference node and adjust a differential voltage according to the offset control signal and a phase comparator configured to receive the adjusted differential voltage and detect a zero current point; a clock generator including a plurality of flip-flops each configured to receive output of a dynamic comparator at a front stage as a clock signal and output the output as clock input of a dynamic comparator at a rear stage, thereby being included in a clock loop as a whole; and an output generator configured to logically sum outputs of the plurality of dynamic comparators and output the sum.

11 . The power converter according to claim 10 , wherein each phase comparator comprises a dynamic latch configured to synchronize with an input clock and output a pulse at a moment when output of the pre-amplifier becomes 0.

12 . The power converter according to claim 11 , wherein, in the clock generator, output of a front flip-flop is connected to reset input of each flip-flop in the clock loop.

13 . A method of controlling power conversion of a power converter comprising an energy storage element, a low-voltage side power switch having one end connected to a common node VX and configured to switch charging of the energy storage element with input power, a high-voltage side power switch having one end connected to the common node and configured to switch discharging of power stored in the energy storage element to a load, a switching controller configured to generate and output switching control signals for controlling on and off states of the high-voltage side power switch and the low-voltage side power switch, and a zero current detection circuit configured to compare outputs of the common node VX and a reference node VR, detect a zero current moment, and output a detection signal to the switching controller, the method comprising:
detecting an error between an output time point of the zero current detection circuit and a falling time of common node output and outputting a corresponding calibration signal to the zero current detection circuit.

14 . The method according to claim 13 , wherein the detecting and outputting comprises:
detecting the falling time of the common node output; detecting an error between output of the zero current detection circuit and the detected falling time; and generating an offset control signal proportional to the detected error and outputting the offset control signal to the zero current detection circuit.

15 . The method according to claim 14 , wherein the generating and outputting an offset control signal comprises:
detecting 41 the error detected in the detecting an error; and counting the duration detected in the detecting duration and outputting a counted value as the offset control signal.

16 . The method according to claim 15 , further comprising:
differentially amplifying, by the zero current detection circuit, voltages of the common node and the reference node and adjusting a differential voltage according to the offset control signal; and receiving, by the zero current detection circuit, the differential voltage and detecting a zero current point.

Assignees

• Skaichips Co Ltd
• Research & Business Found Sungkyunkwan Univ

Inventors

• Lee Kang Yoon
• Oh Ju Won
• Jo Jong Wan
• Lee Sung Jae
• Ha Seung Gyun

Classifications

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• G05F1/565

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• G01R19/175 Primary

  Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title