Power-save mode pulse gating control for switching converter

Patent metadata

Field	Value
Publication number	US-2020119641-A1
Application number	US-201916426942-A
Country	US
Kind code	A1
Filing date	May 30, 2019
Priority date	Oct 15, 2018
Publication date	Apr 16, 2020
Grant date	—

Abstract

An optical communication system includes a light source and an output capacitor coupled to the light source. The system also includes a switching converter circuit coupled to the output capacitor. The switching converter circuit is configured to provide an output voltage to the output capacitor based on an active mode and a power-save mode. The switching converter circuit includes a controller configured to perform pulse gating in the power-save mode based on a timer and a comparison of the output voltage with a voltage threshold.

First claim

What is claimed is:

1 . An optical communication system, comprising:
a light source; an output capacitor coupled to the light source; a switching converter circuit coupled to the output capacitor, wherein the switching converter circuit is configured to provide an output voltage to the output capacitor based on an active mode and a power-save mode, and wherein the switching converter circuit includes a controller configured to perform pulse gating in the power-save mode based on a timer and a comparison of the output voltage with a voltage threshold.

2 . The system of claim 1 , wherein the controller is configured to set a threshold current for a comparator, wherein the comparator is configured to compare the threshold current with an error amplifier output current, and wherein an output of the comparator indicates if the output voltage is lower than the voltage threshold.

3 . The system of claim 2 , wherein the controller is configured to initiate an on-phase in response to the timer indicating an off time is expired and in response to an output of the comparator indicating that the output voltage is less than the voltage threshold.

4 . The system of claim 2 , wherein the controller is configured to add a hysteresis current to the error amplifier output current when the error amplifier output current is greater than the threshold current.

5 . The system of claim 4 , wherein the controller is configured to stop an on-phase in response to an error amplifier current plus the hysteresis current being less than a sense current plus a reference current.

6 . The system of claim 2 , wherein the threshold current is adjusted using a reference current source and a current ramp source.

7 . The system of claim 5 , wherein the comparator is a first comparator, and wherein the controller comprises a second comparator configured to compare the sense current with the error amplifier current.

8 . The system of claim 2 , further comprising:
an AND gate coupled to an output of the comparator and to the timer; a gate driver coupled to an output of the AND gate; and a switch configured to couple or decouple the hysteresis current from the error amplifier output current.

9 . A switching converter circuit, comprising:
an output node; a converter switch coupled between the output node and a ground node; a comparator with a first input node, and a second input node, and an output node, wherein the first input node of the comparator is coupled to an error amplifier output current source, and wherein the second input node of the comparator is coupled to a threshold current source; and an AND gate with a first input node, a second input node, and an output node, wherein the first input node of the AND gate is coupled to the output node of the comparator, the second input node of the AND gate is coupled to a timer, and the output node of the AND gate is coupled to a gate driver for the converter switch.

10 . The switching converter circuit of claim 9 , wherein the threshold current source comprises a reference current source and a current ramp source.

11 . The switching converter circuit of claim 9 , wherein the threshold current source comprises an inductive current sensor at the output node.

12 . The switching converter circuit of claim 9 , wherein the first input node of the comparator is also coupled to a current source configured to provide a hysteresis current via a control switch, and wherein the control switch is coupled to the output node of the AND gate.

13 . The switching converter circuit of claim 12 , wherein the comparator is a first comparator, and wherein the switching converter circuit further comprises a second comparator configured to compare a sense current with the hysteresis current.

14 . A switching converter device, comprising:
an output node; a converter switch coupled between the output node and a ground node; and a controller for the converter switch, wherein the controller is configured to perform pulse gating in a power-save mode based on a timer and a comparison of the output voltage with a voltage threshold.

15 . The switching converter device of claim 14 , wherein the controller comprises a comparator with a first input node, and a second input node, and an output node, wherein the first input node of the comparator is coupled to an error amplifier output current source based on the output voltage, and wherein the second input node of the comparator is coupled to a threshold current source.

16 . The switching converter device of claim 15 , wherein the control further comprises an AND gate with a first input node, a second input node, and an output node, wherein the first input node of the AND gate is coupled to the output node of the comparator, the second input node of the AND date is coupled to a timer, and the output node of the AND gate is coupled to a gate driver for the converter switch.

17 . The switching converter device of claim 15 , wherein the threshold current source comprises a reference current source and a current ramp source.

18 . The switching converter device of claim 15 , wherein the threshold current source comprises a sense current circuit inductively coupled to the output node.

19 . The switching converter device of claim 16 , wherein the first input node of the comparator is also coupled to a hysteresis current source via a control switch.

20 . The switching converter device of claim 19 , wherein the comparator is a first comparator, and wherein the controller further comprises a second comparator configured to compare a sense current with a hysteresis current, wherein an output of the second comparator is provided to a first input node of an RS latch, wherein the output node of the AND gate is coupled to a second input node of the RS latch, and wherein an output node of the RS latch is coupled to the control switch and to a gate driver for the converter switch.

21 . A switching converter controller circuit, comprising:
a current comparator; a first current source coupled to a first input node of the current comparator and configured to provide an error amplifier current to the first input node of the current comparator; a second current source coupled to the first input node of the current comparator and configured to apply a hysteresis current to the first input node of the current comparator via a switch; a sensor coupled to a second input node of the current comparator and configured to provide a sensed output current for the switching converter to the second input node of the current comparator; and an AND gate with a first input node coupled to a timer circuit, wherein the AND gate is configured to control when the output of the current comparator is provided to a driver circuit.

22 . The switching converter controller circuit of claim 21 , wherein the current comparator is a first current comparator, and wherein the switching converter controller circuit further comprises:
a second current comparator with a first input node coupled to the first current source and with a second input node coupled to a second current source and a third current source, wherein the second current source is configured to a provide a reference current, and wherein the third current source is configured to provide a ramp current; a latch circuit with an input node coupled to an output node of the first comparator and with a control node coupled to an output node of the AND gate, wherein the output node of the

Assignees

• Texas Instruments Inc

Inventors

• Liang Jian
• Zhao Wei
• Xiong Weiwei

Classifications

• H02M3/157 Primary

  with digital control · CPC title

• H02M1/15

  using active elements · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H04B10/80

  Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups H04B10/03 - H04B10/70, e.g. optical power feeding or optical transmission through water · CPC title