Integrated circuit device

Patent metadata

Field	Value
Publication number	US-2025210092-A1
Application number	US-202418797883-A
Country	US
Kind code	A1
Filing date	Aug 8, 2024
Priority date	Dec 20, 2023
Publication date	Jun 26, 2025
Grant date	—

Abstract

An integrated circuit device includes a substrate having a cell array area, a peripheral circuit area including a core area, and an interface area between the cell array area and the core area, a cell device isolation film defining cell active regions in the cell array area and having a first depth in a vertical direction, peripheral device isolation films defining peripheral active regions in the peripheral circuit area and each having a second depth greater than the first depth in the vertical direction, an interface device isolation film in the interface area of the substrate, and an active dam surrounding the cell array area, wherein at least a first portion of the active dam is in the core area, and at least a second portion of the active dam is apart from the cell array area with the interface device isolation film therebetween.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
a substrate having a cell array area, a peripheral circuit area, and an interface area, the peripheral circuit area comprising a core area that is adjacent to the cell array area, and the interface area being between the cell array area and the core area; a cell device isolation film arranged in the substrate to define a plurality of cell active regions in the cell array area of the substrate, the cell device isolation film having a first depth in a vertical direction from an upper surface of the substrate; a plurality of peripheral device isolation films arranged in the substrate to define a plurality of peripheral active regions in the peripheral circuit area of the substrate, each of the plurality of peripheral device isolation films having a second depth in the vertical direction from the upper surface of the substrate, the second depth being greater than the first depth; an interface device isolation film in the interface area of the substrate; and an active dam surrounding the cell array area in a plan view, wherein at least a first portion of the active dam is in the core area, and at least a second portion of the active dam is apart from the cell array area with the interface device isolation film therebetween.

2 . The integrated circuit device of claim 1 , wherein, in the plan view, the active dam has a closed-loop shape continuously surrounding the cell array area without interruption.

3 . The integrated circuit device of claim 1 , wherein the core area comprises a sub-word line driver area, which is adjacent to the cell array area in a first horizontal direction, and a sense amplifier area, which is adjacent to the cell array area in a second horizontal direction intersecting with the first horizontal direction, and
the active dam comprises:
a first local region between the interface device isolation film and a first peripheral device isolation film in the sub-word line driver area, the first peripheral device isolation film being closest to the interface device isolation film, among the plurality of peripheral device isolation films; and
a second local region between the interface device isolation film and a second peripheral device isolation film in the sense amplifier area, the second peripheral device isolation film being closest to the interface device isolation film, among the plurality of peripheral device isolation films.

4 . The integrated circuit device of claim 1 , wherein the core area comprises a sub-word line driver area, which is adjacent to the cell array area in a first horizontal direction, and a sense amplifier area, which is adjacent to the cell array area in a second horizontal direction intersecting with the first horizontal direction, and
the active dam comprises:
a first local region between the interface device isolation film and a first peripheral device isolation film in the sub-word line driver area, the first peripheral device isolation film being closest to the interface device isolation film, among the plurality of peripheral device isolation films; and
a second local region in the cell array area facing the sense amplifier area in a horizontal direction, the second local region being between the interface device isolation film and a portion of the cell device isolation film that is closest to the interface device isolation film.

5 . The integrated circuit device of claim 1 , further comprising:
a bit line over the substrate in the cell array area; a wiring pattern apart from the substrate in the vertical direction with the bit line therebetween; and a bit line contact extending in the vertical direction between the bit line and the wiring pattern and configured to be electrically connected to each of the bit line and the wiring pattern, wherein the core area comprises a sub-word line driver area, which is adjacent to the cell array area in a first horizontal direction, and a sense amplifier area, which is adjacent to the cell array area in a second horizontal direction intersecting with the first horizontal direction, the active dam comprises a local region in the cell array area facing the sense amplifier area in the second horizontal direction, the local region being between the interface device isolation film and a portion of the cell device isolation film that is closest to the interface device isolation film, and the local region of the active dam and the bit line contact overlap each other in the vertical direction.

6 . The integrated circuit device of claim 1 , further comprising:
a bit line over the substrate in the cell array area; a wiring pattern apart from the substrate in the vertical direction with the bit line therebetween; and a bit line contact extending in the vertical direction between the bit line and the wiring pattern and configured to be electrically connected to each of the bit line and the wiring pattern, wherein the core area comprises a sub-word line driver area, which is adjacent to the cell array area in a first horizontal direction, and a sense amplifier area, which is adjacent to the cell array area in a second horizontal direction intersecting with the first horizontal direction, the active dam comprises a local region in the cell array area facing the sense amplifier area in the second horizontal direction, the local region being between the interface device isolation film and a portion of the cell device isolation film that is closest to the interface device isolation film, and a distance in the second horizontal direction from the local region of the active dam to the cell array area is smaller than a distance in the second horizontal direction from the bit line contact to the cell array area.

7 . The integrated circuit device of claim 1 , wherein
a sidewall of each of at least some peripheral device isolation films comprises an upper sidewall and a lower sidewall, wherein a distance from the upper surface of the substrate to the lower sidewall is greater than a distance from the upper surface of the substrate to the upper sidewall, and wherein an inclination of the upper sidewall is different from an inclination of the lower sidewall.

8 . The integrated circuit device of claim 1 , further comprising:
a word line at a vertical level, which is lower than a vertical level of the upper surface of the substrate, the word line being in the cell array area and extending lengthwise in a first horizontal direction across the plurality of cell active regions; a wiring pattern over the substrate; and a word line contact extending in the vertical direction between the word line and the wiring pattern, the word line contact being configured to be electrically connected to each of the word line and the wiring pattern, wherein, in the first horizontal direction, the active dam is between the word line contact and a peripheral active region closest to the word line contact, among the plurality of peripheral active regions.

9 . The integrated circuit device of claim 1 , further comprising:
a bit line extending lengthwise in a second horizontal direction over the substrate in the cell array area; a wiring pattern apart from the substrate in the vertical direction with the bit line therebetween; and a bit line contact extending in the vertical direction between the bit line and the wiring pattern, the bit line contact being configured to be electrically connected to each of the bit line and the wiring pattern, wherein, in the second horizontal direction, the active dam is between the bit line contact and a peripheral active region closest to the bit line contact, among the plurality of peripheral active regions.

10 . The integrated

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Minho
• Park Jiho
• Lee Jaemin
• Choi Sena
• Choi Jaybok
• Choi Taeseop
• Ha Yejin
• Park Youngwook
• Hwang Jihyun

Classifications

• H10B12/482

  Bit lines · CPC title

• H10B12/488

  Word lines · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title