Semiconductor device

Patent metadata

Field	Value
Publication number	US-2025203871-A1
Application number	US-202418781730-A
Country	US
Kind code	A1
Filing date	Jul 23, 2024
Priority date	Dec 19, 2023
Publication date	Jun 19, 2025
Grant date	—

Abstract

A semiconductor device may include a substrate, a doped region on the substrate, a gate structure on the substrate, an insulating layer covering the gate structure and the doped region, a first contact extending through the insulating layer and connected to the gate structure, and a first film formation inhibition pattern disposed between the gate structure and the first contact. The first film formation inhibition pattern includes a halogen element.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a doped region on the substrate; a gate structure on the substrate; an insulating layer covering the gate structure and the doped region; a first contact extending through the insulating layer and connected to the gate structure; and a first film formation inhibition pattern disposed between the gate structure and the first contact, wherein the first film formation inhibition pattern includes a halogen element.

2 . The semiconductor device of claim 1 , wherein the gate structure comprises:
a gate insulating pattern; a gate metal pattern on the gate insulating pattern; and a gate capping pattern on the gate metal pattern, wherein the first contact is provided to extend through the insulating layer and the gate capping pattern and is extended to a level that is lower than a bottom surface of the gate capping pattern.

3 . The semiconductor device of claim 2 , wherein the gate metal pattern comprises a recess defined at an upper portion of the gate metal pattern,
wherein the first contact is provided at the recess, wherein the first film formation inhibition pattern is interposed between side and bottom surfaces of the recess and the first contact.

4 . The semiconductor device of claim 2 , wherein the gate capping pattern comprises silicon nitride, and
an interface between the gate capping pattern and the first film formation inhibition pattern includes a halogen element.

5 . The semiconductor device of claim 2 , wherein each of the first contact and the gate metal pattern comprises tungsten.

6 . The semiconductor device of claim 1 , further comprising:
a source/drain pattern extending through the insulating layer and connected to the doped region; and a second film formation inhibition pattern disposed between the insulating layer and the source/drain pattern, wherein the second film formation inhibition pattern includes a halogen element.

7 . The semiconductor device of claim 6 , wherein the source/drain pattern comprises a first portion and a second portion on the first portion,
the second portion is spaced apart from the doped region,
the first and second portions comprise poly silicon,
the doped region includes impurities of a first conductivity type at a first concentration,
the second portion includes impurities of the first conductivity type at a second concentration, and
the first concentration is lower than the second concentration.

8 . The semiconductor device of claim 6 , wherein the doped region comprises a recess defined at an upper portion of the doped region,
the source/drain pattern is provided at the recess, and the second film formation inhibition pattern is spaced apart from a bottom surface of the recess.

9 . The semiconductor device of claim 6 , further comprising a second contact on the source/drain pattern,
wherein the second contact is provided to extend through the insulating layer, and the second contact comprises a metallic material.

10 . The semiconductor device of claim 9 , wherein the second film formation inhibition pattern is extended into a space between the insulating layer and the second contact.

11 . The semiconductor device of claim 1 , wherein the first film formation inhibition pattern is extended into a space between the insulating layer and the first contact.

12 . A semiconductor device, comprising:
a substrate; a doped region on the substrate; a gate structure on the substrate, the gate structure comprising a gate metal pattern; an insulating layer covering the gate structure and the doped region; a first contact extending through the insulating layer and connected to the gate metal pattern; and a first film formation inhibition pattern disposed between the gate metal pattern and the first contact, wherein the first film formation inhibition pattern is in contact with a top surface of the gate metal pattern.

13 . The semiconductor device of claim 12 , wherein the first film formation inhibition pattern is interposed between the first contact and the insulating layer.

14 . The semiconductor device of claim 12 , further comprising:
a source/drain pattern extending through the insulating layer and connected to the doped region; and a second film formation inhibition pattern disposed between the insulating layer and the source/drain pattern, wherein the second film formation inhibition pattern is spaced apart from the doped region.

15 . The semiconductor device of claim 14 , wherein the first and second film formation inhibition patterns comprise the same material.

16 . The semiconductor device of claim 14 , further comprising:
a second contact extending through the insulating layer and disposed on the source/drain pattern; and a junction pattern between the second contact and the source/drain pattern, wherein the second contact comprises a metallic material, the junction pattern comprises silicide, and a level of a top surface of the source/drain pattern is higher than a level of the top surface of the gate metal pattern.

17 . The semiconductor device of claim 14 , wherein the source/drain pattern comprises a first portion and a second portion on the first portion,
the second portion is spaced apart from the doped region,
the first and second portions of the source/drain pattern comprise poly silicon,
the doped region includes impurities of a first conductivity type at a first concentration,
the second portion includes impurities of the first conductivity type at a second concentration, and
the first concentration is lower than the second concentration.

18 . A semiconductor device, comprising:
a substrate; an isolation region on the substrate; a device isolation layer on the isolation region; a doped region on the substrate; a gate structure on the substrate, the gate structure comprising a gate metal pattern; an insulating layer covering the doped region and the gate structure; a gate contact extending through the insulating layer and connected to the gate metal pattern; a source/drain pattern extending through the insulating layer and connected to the doped region; a source/drain contact extending through the insulating layer, connected to the source/drain pattern, and disposed on the source/drain pattern; a first film formation inhibition pattern disposed between the insulating layer and the gate contact; and a second film formation inhibition pattern disposed between the insulating layer and the source/drain pattern, wherein a level of a top surface of the source/drain pattern is higher than a level of a top surface of the gate metal pattern, and the first and second film formation inhibition patterns include a halogen element.

19 . The semiconductor device of claim 18 , wherein the first film formation inhibition pattern is in contact with bottom and side surfaces of the gate contact, and
the second film formation inhibition pattern is in contact with a side surface of the source/drain pattern and is provided to expose a bottom surface of the source/drain pattern.

20 . The semiconductor device of claim 18 , wherein the insulating layer comprises a plurality of layers which are sequentially stacked,
the insulating layer comprises a protection layer in contact with the gate structure, the protection layer comprises silicon nitride, the protection layer is in contact with the first film formation inhibition pattern, and an interface between the protection l

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Byongju
• Kim Youjung

Classifications

• H10D64/027

  by etching at gate locations · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D64/254

  for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts · CPC title

• H10B43/40 Primary

  characterised by the peripheral circuit region · CPC title