Semiconductor devices and methods thereof with selectively formed isolation layers

Patent metadata

Field	Value
Publication number	US-2025201719-A1
Application number	US-202318393890-A
Country	US
Kind code	A1
Filing date	Dec 22, 2023
Priority date	Dec 13, 2023
Publication date	Jun 19, 2025
Grant date	—

Abstract

Semiconductor devices and method for forming the same are provided. The semiconductor devices include a substrate having a frontside and a backside, a source/drain structure disposed on the frontside of the substrate, a backside via that includes a trench filled with a conducting material that is exposed at the backside of the substrate, extends through the substrate, and electrically couples with the source/drain structure, and an isolation layer that includes a dielectric material disposed between and separating the substrate and the backside via, wherein the isolation layer selectively covers a first portion of sidewalls of the trench between the substrate and the backside via and does not cover a second portion of the sidewalls of the trench.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate having a frontside and a backside; a source/drain structure disposed on the frontside of the substrate; a backside via that includes a trench filled with a conducting material that is exposed at the backside of the substrate, extends through the substrate, and electrically couples with the source/drain structure; and an isolation layer that includes a dielectric material disposed between and separating the substrate and the backside via, wherein the isolation layer selectively covers a first portion of sidewalls of the trench between the substrate and the backside via and does not cover a second portion of the sidewalls of the trench.

2 . The semiconductor device of claim 1 , further comprising at least one additional layer formed on the backside of the substrate, wherein the backside via extends through the substrate and the at least one additional layer.

3 . The semiconductor device of claim 1 , wherein the substrate is formed of silicon and the isolation layer is formed of an oxide of silicon (SiO x ) or a nitride of silicon (SiN x ).

4 . The semiconductor device of claim 1 , wherein the isolation layer has a thickness in a range of between 2 and 4 nanometers.

5 . The semiconductor device of claim 1 , wherein the trench has a width in a range of between 5 and 30 nanometers.

6 . The semiconductor device of claim 1 , wherein a ratio of a width of the trench to a thickness of the isolation layer is in a range between 6 and 12.

7 . The semiconductor device of claim 1 , wherein the second portion of the sidewalls of the trench is defined by exposed portions of a shallow trench isolation (STI).

8 . The semiconductor device of claim 1 , further comprising a second source/drain structure disposed on the frontside of the substrate, a plurality of semiconductor layers vertically separated from one another, and a gate structure that is disposed on and wraps around each of the plurality of semiconductor layers, wherein portions of the gate structure disposed between each of the plurality of semiconductor layers contact the source/drain structure and the second source/drain structure.

9 . A method for forming a semiconductor device, the method comprising:
forming a trench through a backside of a substrate of the semiconductor device with a trench opening on the backside of the substrate, wherein a first portion of sidewalls of the trench is formed of first material, a second portion of the sidewalls of the trench is formed of a second material that is different from the first material, and a base of the trench is formed of third material that is different from the first material and the second material; forming a uniform isolation layer on the first portion of the sidewalls of the trench by flowing a fluid into the trench that forms the isolation layer on the first portion of the sidewalls of the trench, does not form the isolation layer on the second portion or the base of the trench; and forming a backside via in the trench that includes a conducting material that is exposed at the backside of the substrate, extends through the substrate, and electrically couples with a source/drain structure of the semiconductor device.

10 . The method of claim 9 , wherein the first material is silicon and the isolation layer is formed of a dielectric material that includes an oxide of silicon (SiO x ) or a nitride of silicon (SiN x ).

11 . The method of claim 9 , wherein the isolation layer has a thickness in a range of between 2 and 4 nanometers.

12 . The method of claim 9 , wherein the trench has a width in a range of between 5 and 30 nanometers.

13 . The method of claim 9 , wherein forming the isolation layer includes flowing the fluid at a flow rate in a range of 1 and 20 sccm while providing a pressure in a range of 10 and 100 torr at a power in a range of 500 to 2000 watts for a time in a range of 60 to 360 seconds.

14 . The method of claim 9 , further comprising:
planarizing the backside of the substrate; forming a first masking layer on the backside of the substrate; forming a second masking layer on the first masking layer, wherein forming the trench includes performing a photolithography and etching process to form the trench through the first masking layer and the second masking layer; etching the third material at the base of the trench after forming the isolation layer to expose a portion of the source/drain structure; forming a silicide deposit disposed at the base of the trench that is electrically coupled with the source/drain structure; and removing the second masking layer after forming the backside via by a chemical mechanical polishing process.

15 . A method for forming a semiconductor device, the method comprising:
forming a trench through a backside of a substrate of the semiconductor device with a trench opening at the backside of the substrate, wherein a first portion of sidewalls of the trench is formed of first material, at least a second portion of the sidewalls of the trench is formed of a second material that is different from the first material, and a base of the trench is formed of third material that is different from the first material and the second material; flowing a fluid into the trench that forms a uniform isolation layer on the first portion of the sidewalls of the trench and on the base of the trench, and does not form the isolation layer on the second portion of the sidewalls of the trench; removing a portion of the isolation layer covering the base of the trench to expose a portion of a source/drain structure; and forming a backside via in the trench that includes a conducting material that is exposed at the backside of the substrate, extends through the substrate, and electrically couples with the source/drain structure of the semiconductor device.

16 . The method of claim 15 , wherein the first material is silicon and the isolation layer is formed of a dielectric material that includes an oxide of silicon (SiO x ) or a nitride of silicon (SiN x ).

17 . The method of claim 15 , wherein the isolation layer has a thickness in a range of between 2 and 4 nanometers.

18 . The method of claim 15 , wherein the trench has a width in a range of between 5 and 30 nanometers.

19 . The method of claim 15 , wherein forming the isolation layer includes flowing the fluid at a flow rate in a range of 1 and 20 sccm while providing a pressure in a range of 10 and 100 torr at a power in a range of 500 to 2000 watts for a time in a range of 60 to 360 seconds.

20 . The method of claim 15 , further comprising:
planarizing the backside of the substrate; forming a first masking layer on the backside of the substrate; forming a second masking layer on the first masking layer, wherein forming the trench includes performing a photolithography and etching process to form the trench through the first masking layer and the second masking layer; forming a silicide deposit disposed at the base of the trench that is electrically coupled with the source/drain structure after removing the portion of the isolation layer covering the base of the trench; and removing the second masking layer after forming the backside via by a chemical mechanical polishing process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Po-Yu
• Wu Shih-Chieh
• Wu I-Wen
• Lee Chen-Ming
• Wang Mei-Yun

Classifications

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H01L21/76898

  Electricity · mapped topic