Interconnect substrate and method of making the same

Patent metadata

Field	Value
Publication number	US-2025201718-A1
Application number	US-202418971694-A
Country	US
Kind code	A1
Filing date	Dec 6, 2024
Priority date	Dec 15, 2023
Publication date	Jun 19, 2025
Grant date	—

Abstract

An interconnect substrate includes a first insulating layer having a cavity formed therein, an electronic component including an insulating substrate and a pad provided on one side of the insulating substrate, the electronic component being arranged in the cavity, with the pad facing an opening of the cavity, and a second insulating layer disposed on the first insulating layer and in the cavity, wherein an upper surface and side surfaces of the pad have areas situated outside the insulating substrate, wherein at least a part of the areas is covered with the second insulating layer, and wherein a roughness a surface of the pad covered with the second insulating layer is larger than a roughness of a surface of the pad not covered with the second insulating layer.

First claim

What is claimed is:

1 . An interconnect substrate comprising:
a first insulating layer having a cavity formed therein; an electronic component including an insulating substrate and a pad provided on one side of the insulating substrate, the electronic component being arranged in the cavity, with the pad facing an opening of the cavity; and a second insulating layer disposed on the first insulating layer and in the cavity, wherein an upper surface and side surfaces of the pad have areas situated outside the insulating substrate, wherein at least a part of the areas is covered with the second insulating layer, and wherein a roughness of a surface of the pad covered with the second insulating layer is larger than a roughness of a surface of the pad not covered with the second insulating layer.

2 . The interconnect substrate as claimed in claim 1 , wherein the pad is formed of a same material as a single seamless structure.

3 . The interconnect substrate as claimed in claim 1 , wherein a via hole penetrates through the second insulating layer to reach a part of the upper surface of the pad, and the roughness of the surface of the pad covered with the second insulating layer is larger than a roughness of the part of the upper surface of the pad situated in the via hole.

4 . The interconnect substrate as claimed in claim 1 , wherein an entirety of the side surfaces of the pad is situated outside the insulating substrate and covered with the second insulating layer.

5 . The interconnect substrate as claimed in claim 4 , comprising two of said pads which are adjacent to each other, wherein a recess for exposing portions of outer peripheral areas of lower surfaces of the pads is provided in the insulating substrate, and an entirety of side surfaces of the pads and the portions of the outer peripheral areas of the lower surfaces are covered with the second insulating layer.

6 . The interconnect substrate as claimed in claim 5 , wherein in a cross-sectional view, a depth of the recess is deepest in a midpoint area between the pads, and becomes shallower with distance from the midpoint area.

7 . The interconnect substrate as claimed in claim 1 , wherein the insulating substrate is made of a material having an etching rate higher than an etching rate of the pad in plasma etching using a fluorine-based etching gas.

Assignees

• Shinko Electric Ind Co

Inventors

• Arai Takashi

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10W20/47 Primary

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• H05K3/4626

  characterised by the insulating layers or materials (H05K3/4688 takes precedence) · CPC title