Pixel circuit, driving method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-2025201179-A1
Application number	US-202418984014-A
Country	US
Kind code	A1
Filing date	Dec 17, 2024
Priority date	Dec 18, 2023
Publication date	Jun 19, 2025
Grant date	—

Abstract

A first data write module of a pixel circuit, in response to an effective potential of a first control signal, writes a global data voltage on a first global signal line to a gate node of a drive module in a write frame and at least one retention frame to increase the frequency of writing data or prolong the duration of writing data at the gate node of the drive module during a low-frequency image refresh. A second data write module of the pixel circuit, in response to an effective potential of a second control signal, writes a data control voltage on a data line to a control node in the write frame to enable the control node to have a control potential, and maintains the potential of the control node at the control potential in the retention frame.

First claim

What is claimed is:

1 . A pixel circuit, comprising:
a drive module, a first light emission control module, and a light-emitting module sequentially connected in series, wherein the drive module has a gate node, and the first light emission control module has a control node; a first data write module, which is coupled between a first global signal line and the drive module and configured to, in response to an effective potential of a first control signal, write a global data voltage on the first global signal line to the gate node; and a second data write module, which is coupled between a data line and the control node and configured to, in response to an effective potential of a second control signal, write a data control voltage on the data line to the control node to enable the control node to have a control potential.

2 . The pixel circuit according to claim 1 , wherein one display cycle of the pixel circuit comprises at least one write frame, and the second data write module is configured to, in response to the effective potential of the second control signal, write the data control voltage on the data line to the control node in the at least one write frame to enable the control node to have the control potential.

3 . The pixel circuit according to claim 1 , wherein the first light emission control module is controlled by the data control voltage to be turned on or turned off.

4 . The pixel circuit according to claim 2 , wherein the first light emission control module comprises a first light emission control transistor, and a gate of the first light emission control transistor is electrically connected to the control node;
the data control voltage is configured to enable the first light emission control transistor to operate in a linear region when the first light emission control transistor is controlled to be turned on by the data control voltage.

5 . The pixel circuit according to claim 2 , wherein the second data write module comprises a write unit and a storage unit, and the write unit and the storage unit are electrically connected to the control node, the display cycle further comprises at least one retention frame, the second data write module is further configured to maintain a potential of the control node at the control potential in the at least one retention frame; wherein:
the write unit is configured to, in response to the effective potential of the second control signal, write the data control voltage on the data line to the control node in the at least one write frame to enable the control node to have the control potential; the storage unit is configured to maintain the potential of the control node at the control potential in the at least one retention frame; and the write unit comprises a first dual-gate transistor, a gate of the first dual-gate transistor accesses the second control signal, a source of the first dual-gate transistor is coupled to the data line, and a drain of the first dual-gate transistor is coupled to the control node.

6 . The pixel circuit according to claim 2 , wherein when the display cycle comprises one write frame and a plurality of retention frames,
the effective potential of the first control signal is configured to be generated in the write frame and at least one of the plurality of retention frames, or, the first control signal is configured to be maintained at the effective potential in at least one of the plurality of retention frames; and the effective potential of the second control signal is configured to be generated in the write frame.

7 . The pixel circuit according to claim 6 , wherein the drive module has a source node, and when the effective potential of the first control signal is configured to be generated in the write frame and the at least one of the plurality of retention frames, the first data write module is coupled to the source node; or
when the first control signal is configured to be maintained at the effective potential in the at least one of the plurality of retention frames, the first data write module is coupled to the gate node.

8 . The pixel circuit according to claim 2 , wherein when the display cycle comprises a plurality of write frames,
the first data write module is configured to be coupled between the data line and the drive module and, in response to the effective potential of the first control signal, write a grayscale data voltage on the data line to the gate node; and the second data write module is configured to be coupled between a second global signal line and the control node and, in response to the effective potential of the second control signal, write a global control voltage on the second global signal line to the control node to enable the control node to have the control potential.

9 . The pixel circuit according to claim 8 , wherein the display cycle further comprises at least one retention frame, wherein:
the effective potential of the first control signal is configured to be generated in each of the plurality of write frames and the at least one retention frame, and the effective potential of the second control signal are configured to be generated in each of the plurality of write frames; the grayscale data voltage corresponds to a display grayscale, and voltage values of grayscale data voltages corresponding to different display grayscales of a same display brightness level are different; or when the display cycle comprises one write frame and a plurality of retention frames, the global data voltage corresponds to a display brightness level, voltage values of a global data voltage corresponding to a same display brightness level are the same, and voltage values of global data voltages corresponding to different display brightness levels are different; and the data control voltage has a first potential and a second potential, and the global control voltage has a third potential, wherein the first potential and the third potential are configured to enable the first light emission control module to be turned on, and the second potential is configured to enable the first light emission control module to be turned off.

10 . The pixel circuit according to claim 2 , wherein when the display cycle comprises a plurality of write frames,
the first data write module is configured to be coupled between the first global signal line and the drive module and, in response to the effective potential of the first control signal, write the global data voltage to the gate node; the second data write module is configured to be coupled between the data line and the control node and, in response to the effective potential of the second control signal, write the data control voltage to the control node to enable the control node to have the control potential.

11 . The pixel circuit according to claim 10 , wherein at least one of the following configurations is satisfied:
the effective potential of the first control signal and the effective potential of the second control signal are configured to be generated in each of the plurality of write frames; or when one display cycle comprises a plurality of write frames or comprises one write frame and a plurality of retention frames, the global data voltage corresponds to a display brightness level, voltage values of the global data voltage corresponding to a same display brightness level are the same, and voltage values of global data voltages corresponding to different display brightness levels are different; and the data control voltage has a first potential and a second potential, wherein the first potential is configured to enable the first light emission control module to be turned on, and the second potential is configured to enable

Assignees

• Visionox Tech Inc
• Yungu Gu’An Tech Co Ltd

Inventors

• Gai Cuili
• Zhang Deqiang
• Zhu Xiujian
• Gao Xiaoyu
• Guo Enqing
• Li Junfeng

Classifications

• G09G2330/021

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