Pixel driving circuit and display panel

US12165589B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12165589-B2
Application numberUS-202318350227-A
CountryUS
Kind codeB2
Filing dateJul 11, 2023
Priority dateJun 30, 2021
Publication dateDec 10, 2024
Grant dateDec 10, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel circuit, a driving method, and a display panel. The pixel circuit includes a driving module, a data write module, a first compensation module, a second compensation module, a light-emitting module, a storage module, and a coupling module. The data write module is configured to write a voltage related to a data voltage to a control terminal of the driving module. The driving module is configured to provide a drive signal for the light-emitting module according to the voltage of the control terminal to drive the light-emitting module to emit light. A first terminal of the second compensation module is connected to the control terminal of the driving module, a second terminal of the second compensation module is connected to a first terminal of the first compensation module, and a second terminal of the first compensation module is connected to a first terminal of the driving module.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel driving circuit, comprising: a driving module configured to generate a driving current; a light-emitting module configured to emit light in response to the drive current; a threshold compensation module configured to compensate for a threshold voltage of the driving module in a charging stage, wherein the threshold compensation module is connected between an anti-leakage node and a control terminal of the driving module; a first initialization module configured to initialize the control terminal of the driving module in an initialization stage, wherein the first initialization module is connected between an initialization signal input terminal and the anti-leakage node; a first holding module configured to hold a potential of the anti-leakage node; a second holding module configured to hold a potential of a first terminal of the driving module; and a first blocking module configured to block a conduction path between the anti-leakage node and the light-emitting module in a light-emitting stage. 2. The pixel driving circuit of claim 1 , wherein a first terminal of the first holding module is connected to a fixed signal, and a second terminal of the first holding module is electrically connected to the anti-leakage node. 3. The pixel driving circuit of claim 1 , further comprising: a data write module configured to write a voltage corresponding to a data signal to a control terminal of the driving module in a charging stage; and a storage module configured to maintain a potential of the control terminal of the driving module. 4. The pixel driving circuit of claim 3 , wherein a first terminal of the first initialization module is electrically connected to the initialization signal input terminal, and a control terminal of the first initialization module is electrically connected to a first scan signal input terminal of the pixel driving circuit; a first terminal of the data write module is electrically connected to a data signal input terminal of the pixel driving circuit, a second terminal of the data write module is electrically connected to a first terminal of the driving module, and a control terminal of the data write module is electrically connected to a second scan signal input terminal of the pixel driving circuit; a first terminal of the storage module is electrically connected to a first power-supply signal input terminal of the pixel driving circuit, and a second terminal of the storage module is electrically connected to the control terminal of the driving module; the pixel driving circuit further comprises a first light-emitting control module and a second light-emitting control module, wherein a first terminal of the first light-emitting control module is electrically connected to the first power-supply signal input terminal, a second terminal of the first light-emitting control module is electrically connected to the first terminal of the driving module, and a control terminal of the first light-emitting control module is electrically connected to an enable signal input terminal of the pixel driving circuit; a first terminal of the second light-emitting control module is electrically connected to a second terminal of the driving module, a second terminal of the second light-emitting control module is electrically connected to a first terminal of the light-emitting module, and a control terminal of the second light-emitting control module is electrically connected to the enable signal input terminal; and a second terminal of the light-emitting module is electrically connected to a second power-supply signal input terminal of the pixel driving circuit; and a first terminal of the first holding module is electrically connected to the initialization signal input terminal or the first power-supply signal input terminal, and a second terminal of the first holding module is electrically connected to the anti-leakage node. 5. The pixel driving circuit of claim 4 , wherein a first terminal of the first blocking module is electrically connected to the anti-leakage node, a second terminal of the first blocking module is electrically connected to a second terminal of the first initialization module and the second terminal of the driving module, and a control terminal of the first blocking module is electrically connected to the second scan signal input terminal; and a first terminal of the threshold compensation module is electrically connected to the control terminal of the driving module, a second terminal of the threshold compensation module is electrically connected to the anti-leakage node, and a control terminal of the threshold compensation module is electrically connected to the second scan signal input terminal. 6. The pixel driving circuit of claim 5 , wherein the charging stage at least partially overlaps the initialization stage. 7. The pixel driving circuit of claim 4 , wherein a first terminal of the threshold compensation module is electrically connected to the control terminal of the driving module, a second terminal of the threshold compensation module is electrically connected to the anti-leakage node, and a control terminal of the threshold compensation module is electrically connected to a long scan signal input terminal of the pixel driving circuit; a first terminal of the first blocking module is electrically connected to the anti-leakage node, a second terminal of the first blocking module is electrically connected to the second terminal of the driving module, and the control terminal of the first blocking module is electrically connected to the second scan signal input terminal or the long scan signal input terminal, wherein the long scan signal input terminal is set to input a conduction signal in each of the initialization stage and the charging stage. 8. The pixel driving circuit of claim 7 , wherein a duration of a pulse width of a long scan signal covers at least the initialization stage and the charging stage. 9. The pixel driving circuit of claim 7 , wherein the control terminal of the first blocking module is electrically connected to the long scan signal input terminal; and the second holding module is further configured to hold a potential of the first terminal of the driving module, and the long scan signal input terminal is set to input a conduction signal of a preset time between the charging stage and the light-emitting stage. 10. The pixel driving circuit of claim 4 , further comprising: a second blocking module and a third blocking module, wherein a first terminal of the threshold compensation module is electrically connected to the control terminal of the driving module, a second terminal of the threshold compensation module is electrically connected to the anti-leakage node, and a control terminal of the threshold compensation module is electrically connected to a long scan signal input terminal of the pixel driving circuit; a first terminal of the first blocking module is electrically connected to the anti-leakage node, a second terminal of the first blocking module is electrically connected to a first terminal of the second blocking module, and a control terminal of the first blocking module is electrically connected to the long scan signal input terminal; a second terminal of the second blocking module is electrically connected to the second terminal of the driving module, a control terminal of the second blocking module is electrically connected to the second scan signal input terminal of the pixel driving circuit; and a first terminal of the third blocking module is electrically connected to the anti-leakage node, a second terminal of the third blocking module is electrically connected to a second terminal of the first initialization module

Assignees

Inventors

Classifications

  • Change or adaptation of the frame rate of the video stream · CPC title

  • Details of drivers for scan electrodes · CPC title

  • Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

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What does patent US12165589B2 cover?
A pixel circuit, a driving method, and a display panel. The pixel circuit includes a driving module, a data write module, a first compensation module, a second compensation module, a light-emitting module, a storage module, and a coupling module. The data write module is configured to write a voltage related to a data voltage to a control terminal of the driving module. The driving module is co…
Who is the assignee on this patent?
Yungu Guan Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Dec 10 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).