Display device and controller

Patent metadata

Field	Value
Publication number	US-2025201166-A1
Application number	US-202418924808-A
Country	US
Kind code	A1
Filing date	Oct 23, 2024
Priority date	Dec 18, 2023
Publication date	Jun 19, 2025
Grant date	—

Abstract

A display device can include a display panel having a plurality of subpixels, a memory storing image control data for controlling an image displayed on the display panel, a mode control signal generation circuit generating a mode control signal based on a first mode signal supplied from a first controller, and a second controller configured to share the memory with the first controller and determine a control authority of the first controller for the memory through the mode control signal.

First claim

What is claimed:

1 . A display device, comprising:
a display panel configured to display an image; a memory configured to store image control data for controlling the image displayed on the display panel; a mode control signal generation circuit configured to generate a mode control signal based on a first mode signal supplied from a first controller; and a second controller configured to share the memory with the first controller and determine a control authority of the first controller for the memory through the mode control signal.

2 . The display device of claim 1 , wherein the image control data includes gamma data for controlling a luminance of the image displayed on the display panel.

3 . The display device of claim 1 , wherein the first controller is a host controller, and the second controller is a timing controller.

4 . The display device of claim 1 , wherein the first controller includes a master buffer configured to transfer an external control signal to the memory,
wherein the display device further comprises a slave buffer configured to transfer an internal control signal to the memory, the slave buffer being positioned inside the second controller or on a control printed circuit board outside the second controller, and wherein the master buffer and the slave buffer are controlled by the mode control signal.

5 . The display device of claim 4 , wherein the mode control signal maintains the master buffer in a turn-on state and the slave buffer in a high-impedance state in a first mode period in which the first controller controls the memory.

6 . The display device of claim 4 , wherein the mode control signal maintains the master buffer in a high-impedance state and the slave buffer in a turn-on state in a second mode period in which the second controller controls the memory.

7 . The display device of claim 1 , wherein the first mode signal includes:
a mode enable signal configured to indicate entry into a first mode in which the first controller controls the memory; and a chip selection signal configured to select, for the first controller, a chip in the memory in the first mode.

8 . The display device of claim 7 , wherein the mode control signal generation circuit includes:
a first edge detection circuit configured to generate a mode enable edge signal by detecting an edge where the mode enable signal is turned on; a second edge detection circuit configured to generate a chip selection edge signal by detecting an edge where the chip selection signal is turned off; a first logic gate configured to generate the mode control signal using the mode enable edge signal and the chip selection edge signal; and a second logic gate configured to generate a reset signal for a reset operation of the first edge detection circuit and the second edge detection circuit using the mode enable edge signal and the chip selection edge signal.

9 . The display device of claim 8 , wherein the first edge detection circuit is a flip-flop circuit for receiving the mode enable signal through a clock terminal.

10 . The display device of claim 8 , wherein the second edge detection circuit is a flip-flop circuit receiving the chip selection signal through a clock terminal.

11 . The display device of claim 8 , wherein the first logic gate is an XOR gate.

12 . The display device of claim 8 , wherein the second logic gate is an AND gate.

13 . The display device of claim 8 , wherein the mode control signal generation circuit further includes a reset buffer configured to delay the reset signal for a predetermined time.

14 . The display device of claim 1 , wherein the mode control signal generation circuit is positioned in the second controller.

15 . The display device of claim 1 , wherein the mode control signal generation circuit is positioned on a control printed circuit board.

16 . The display device of claim 8 , wherein when entering the first mode, the mode enable signal is first changed to a turn-on level, and then the chip selection signal is changed to a turn-on level.

17 . The display device of claim 8 , wherein when entering a second mode in which the second controller controls the memory, the chip selection signal is first changed to a turn-off level, and then the mode enable signal is changed to a turn-off level.

18 . A timing controller, comprising:
a first edge detection circuit configured to generate a mode enable edge signal by detecting an edge where a mode enable signal supplied from a host controller is turned on; a second edge detection circuit configured to generate a chip selection edge signal by detecting an edge where a chip selection signal supplied from the host controller is turned off; a first logic gate configured to generate a mode control signal for determining a control authority of the host controller for a memory using the mode enable edge signal and the chip selection edge signal; and a second logic gate configured to generate a reset signal for a reset operation of the first edge detection circuit and the second edge detection circuit using the mode enable edge signal and the chip selection edge signal, wherein the timing controller shares the memory with the host controller.

19 . The timing controller of claim 18 , further comprising a slave buffer configured to transfer an internal control signal to the memory,
wherein the host controller comprises a master buffer configured to transfer an external control signal to the memory, and the master buffer and the slave buffer are controlled by the mode control signal.

20 . The timing controller of claim 19 , wherein the mode control signal maintains the master buffer in a turn-on state and the slave buffer in a high-impedance state in a first mode period in which the host controller controls the memory.

21 . The timing controller of claim 19 , wherein the mode control signal maintains the master buffer in a high-impedance state and the slave buffer in a turn-on state in a second mode period in which the timing controller controls the memory.

22 . A display system comprising:
the display device of claim 1 , wherein the display panel includes a plurality of subpixels configured to display the image; and the first controller connected to the display device.

Assignees

• Lg Display Co Ltd

Inventors

• Shin Beomjun
• Ryu Gyeongho

Classifications

• G09G2360/127

  Updating a frame memory using a transfer of data from a source area to a destination area · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2360/12

  Frame memory handling · CPC title