Processor and memory control method

Patent metadata

Field	Value
Publication number	US-2016196206-A1
Application number	US-201414909443-A
Country	US
Kind code	A1
Filing date	Jul 30, 2014
Priority date	Jul 30, 2013
Publication date	Jul 7, 2016
Grant date	—

Abstract

The present invention relates to a processor and a memory. More specifically, the present invention relates to a switchable on chip memory accessible by various master intellectual properties (IPs) and a method for controlling the same, and the method for controlling the on chip memory, according to one embodiment of the present invention, can comprise the steps of: setting memory allocation information including at least one among modes of respective master IPs, priority, space size of a required memory, and correlation with other master IPs; and allocating memories for the respective master IPs by using the memory allocation information. According to the one embodiment of the present invention, various master IPs within an embedded SoC are capable of utilizing all of the advantages of an on chip buffer and an on chip cache.

First claim

1 . A memory control method of an on-chip memory, the memory control method comprising:
setting memory allocation information including at least one of modes according to individual master devices, a priority, a required size of memory space, or a correlation with another master device; and allocating memories to the individual master devices using the memory allocation information.

2 . The memory control method of claim 1 , wherein setting the memory allocation information comprises:
determining whether the locality of a master device of the master devices exists; determining, when the locality of the master device exists of the master devices, whether an access region is less than the memory area of the on-chip memory; setting a master device mode to a buffer when an access region is less than the memory area of the on-chip memory; and setting the master mode to a cache when an access region is greater than the memory area of the on-chip memory.

3 . The memory control method of claim 1 , wherein setting the memory allocation information comprises:
setting, when a master device of the master device is a real-time device, the master device of the master devices to have a high priority.

4 . The memory control method of claim 1 , wherein setting the memory allocation information comprises:
when a master device mode is a buffer, setting a required size of memory space according to the access region size; and when the master device mode is a cache, setting a spot where a hit ratio is identical to a preset threshold as a required size of memory space.

5 . The memory control method of claim 1 , wherein setting the memory allocation information comprises:
when a ratio of a time that two master devices simultaneously operate to a time that one of the master devices operates is greater than or equal to a preset threshold, setting the correlation between the master devices to be high.

6 . The memory control method of claim 1 , wherein allocating memories to the individual master IPs comprises:
selecting a master device with the highest priority; determining whether the correlation between the selected master device and a master device that has been selected before the selected master device is high; and allocating memories to the master devices according to a required size of memory space, when the correlation between the selected master device and the master device that has been selected before the selected master device is not high.

7 . The memory control method of claim 6 , wherein allocating the memories to the individual master IPs comprises:
when the correlation between the selected master IP and the master device that has been selected before the selected master device is high, determining whether the summation of a memory space size, required by the selected master device, and memory space sizes, allocated to the other master devices selected previously before the selected master device, is greater than the memory area size of the on-chip memory; when the summation of a memory space size is less than the memory area size of the on-chip memory, allocating memories to the master devices according to the required memory space size; and when the summation of a memory space size is greater than the memory area size of the on-chip memory, allocating memories to the master devices according to a size produced by subtracting the memory space size from the memory area size of the on-chip memory.

8 . The memory control method of claim 1 , wherein the memory allocation is performed in a unit of chunk.

9 . A memory control method of an on-chip memory of a processor comprising:
setting memory allocation information including at least one of modes according to individual master devices, a priority, a required size of memory space, or a correlation with another master device; and allocating memories to the individual master devices using the memory allocation information.

10 . The memory control method of claim 9 , wherein the memory allocation is performed in a unit of chunk.

11 . An on-chip memory comprising:
a memory space; and a controller configured to:
set memory allocation information including at least one of modes according to individual master devices, a priority, a required size of memory space, or a correlation with another master device; and
allocate memories to the individual master devices using the memory allocation information.

12 . The on-chip memory of claim 11 , wherein the controller is further configured to:
determine whether the locality of a master device of the master devices exists; determine, when the locality of a master device of the master devices exists, whether an access region is less than the memory area of the on-chip memory; set a master device mode to a buffer when an access region is less than the memory area of the on-chip memory; and set a master device mode to a cache when an access region is greater than the memory area of the on-chip memory.

13 . The on-chip memory of claim 11 , wherein the controller is configured to set, when a master device of the master devices is a real-time device, the master device to have a high priority.

14 . The on-chip memory of claim 11 , wherein the controller is further configured to:
set, when a master device mode is a buffer, a required size of memory space according to the access region size; and set, when the master device mode is a cache, a spot where a hit ratio is identical to a preset threshold as a required size of memory space.

15 . The on-chip memory of claim 11 , wherein, when a ratio of a time that two master devices simultaneously operate to a time that one of the master devices operates is greater than or equal to a preset threshold, the controller is configured to set the correlation between the master devices to be high.

16 . The on-chip memory of claim 11 , wherein the controller is configured to:
select a master device with the highest priority; determine whether the correlation between the selected master device and a master device that has been selected before the selected master device is high; and allocate memories to the master devices according to a required size of memory space, when the correlation between the selected master device and the master device that has been selected before the selected master device is not high.

17 . The on-chip memory of claim 16 , wherein:
when the correlation between the selected master device and the master device that has been selected before the selected master device is high, the controller is configured to determine whether the summation of a memory space size, required by the selected master device, and memory space sizes, allocated to the master devices selected previously before the selected master device, is greater than the memory area size of the on-chip memory; when the summation of a memory space size is less than the memory area size of the on-chip memory, the controller is configured to allocate memories to the master IPs according to the required memory space size; and when the summation of a memory space size is greater than the memory area size of the on-chip memory, the controller is configured to allocate memories to the master devices according to a size produced by subtracting the memory space size from the memory area size of the on-chip memory.

18 . The on-chip memory of claim 11 , wherein the memory allocation is performed in a unit of chunk.

19 . A processor comprising:
at least one master device; and an on-chip memory, whe

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Byoungik
• Park Jinyoung
• Lee Seungwook
• Hong Eunseok

Classifications

• G06F13/1694

  Configuration of memory controller to different memory types · CPC title

• G06F13/18

  based on priority control (G06F13/1605 takes precedence) · CPC title

• G06F12/023 Primary

  Free address space management · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F13/1663

  Access to shared memory · CPC title