Methods and Devices to Improve Switching Time by Bypassing Gate Resistor

Patent metadata

Field	Value
Publication number	US-2025192766-A1
Application number	US-202519017139-A
Country	US
Kind code	A1
Filing date	Jan 10, 2025
Priority date	Dec 12, 2016
Publication date	Jun 12, 2025
Grant date	—

Abstract

Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

First claim

1 . (canceled)

2 . A switching circuit comprising:
a series arrangement of main switches; a resistive network having a common node, the resistive network comprising main gate resistors, each main gate resistor coupling the common node to a corresponding main switch, and a series arrangement of bypass elements coupling an input terminal to the common node of the resistive network, each bypass element comprising a bypass switch coupled in parallel with a corresponding bypass gate resistor.

3 . The switching circuit of claim 2 , wherein the main switches comprise field-effect transistors (FETs).

4 . The switching circuit of claim 3 , wherein the main switches are configured in a stacked arrangement, each main switch having a corresponding gate resistor coupled between a common node and a gate terminal of the main switch.

5 . The switching circuit of claim 2 , wherein each bypass element is configured to be open when the main switches are in either an OFF or an ON state and to be closed during a transition between the OFF and ON states.

6 . The switching circuit of claim 5 , wherein each bypass element includes a gate resistor coupled between an input terminal and a control terminal of the bypass switch.

7 . The switching circuit of claim 2 , wherein the bypass elements comprise NMOS and PMOS transistors, wherein the drain and source terminals of each NMOS transistor are coupled to the corresponding drain and source terminals of a PMOS transistor.

8 . The switching circuit of claim 7 , wherein each bypass element comprises a pair of series-coupled resistors connected to the gate terminals of the NMOS and PMOS transistors.

9 . The switching circuit of claim 8 , wherein a control voltage applied to the input terminal is configured to control the bypass elements by selectively enabling or disabling the bypass elements.

10 . The switching circuit of claim 9 , wherein the control voltage applied to the bypass elements varies based on operational states of the main switches.

11 . The switching circuit of claim 2 , wherein a bypass switch of the bypass elements includes multiple switches arranged in a cascade configuration.

12 . A switching device comprising:
a plurality of main switching elements arranged in series; a resistive network comprising gate resistors, each gate resistor connecting a common node to a terminal of a corresponding main switching element; a plurality of bypass elements, each bypass element including one or more bypass switches coupled in parallel with a corresponding bypass resistor; a control circuit configured to selectively activate the one or more bypass switches to dynamically adjust an impedance between the common node an input node.

13 . The switching device of claim 12 , wherein the main switching elements comprise NMOS transistors.

14 . The switching device of claim 12 , wherein the one or more bypass switches include FET switches.

15 . The switching device of claim 12 , wherein the one or more bypass switches include at least one NMOS switch and one PMOS switch.

16 . The switching device of claim 12 , wherein the control circuit is configured to receive a supply voltage that selectively activates the one or more bypass switches during transition phases of the main switching elements.

17 . The switching device of claim 12 , wherein the control circuit applies distinct voltage levels to control operational states of bypass elements.

18 . The switching device of claim 12 , wherein each of the one or more bypass switches is configured to be open when the main switching elements are in either an OFF or an ON state and to be closed only when the main switching elements are transitioning from an OFF to an ON state.

19 . The switching device of claim 12 , wherein the plurality of bypass elements are arranged in a stacked configuration to distribute voltage stress across bypass switches.

20 . The switching device of claim 19 , wherein the multiple bypass switches operate in alternating conduction states based on a control voltage applied to an input terminal.

21 . The switching device of claim 12 , wherein the plurality of bypass elements are selectively disabled when the main switching elements are fully turned ON or OFF.

Assignees

• Psemi Corp

Inventors

• Shanjani Payman
• Shapiro Eric S

Classifications

• H03K17/04123 Primary

  in field-effect transistor switches · CPC title