Semiconductor package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2025192011-A1
Application number	US-202318533136-A
Country	US
Kind code	A1
Filing date	Dec 7, 2023
Priority date	Dec 7, 2023
Publication date	Jun 12, 2025
Grant date	—

Abstract

A semiconductor package includes a package substrate, an integrated interconnect structure, an optical engine module, and an integrated circuit package. The integrated interconnect structure is bonded over the package substrate and includes an insulation body, a plurality of through vias extending through the insulation body. The optical engine module includes an electronic die, a photonic die, and a waveguide. A portion of the optical engine module is embedded in the integrated interconnect structure. The integrated circuit package is bonded over the integrated interconnect structure and electrically coupled to the optical engine module.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a package substrate; an integrated interconnect structure bonded over the package substrate and comprising an insulation body and a plurality of through vias extending through the insulation body; an optical engine module comprising an electronic die, a photonic die, and a waveguide, wherein a portion of the optical engine module is embedded in the integrated interconnect structure; and an integrated circuit package bonded over the integrated interconnect structure and electrically coupled to the optical engine module.

2 . The semiconductor package as claimed in claim 1 , wherein the electronic die and the waveguide are embedded in the integrated interconnect structure, and the photonic die stacked over the electronic die and the waveguide.

3 . The semiconductor package as claimed in claim 2 , wherein the electronic die is connected to photonic die and the integrated circuit package.

4 . The semiconductor package as claimed in claim 1 , wherein the waveguide comprises an optical dielectric waveguide.

5 . The semiconductor package as claimed in claim 1 , further comprises an interconnect device embedded in the integrated interconnect structure, and the interconnect device is connected to the electronic die and the integrated circuit package.

6 . The semiconductor package as claimed in claim 5 , wherein the waveguide is embedded in the integrated interconnect structure.

7 . The semiconductor package as claimed in claim 6 , wherein the electronic die is bonded over the integrated interconnect structure and electrically coupled to the interconnect device, and the photonic die is stacked over the electronic die and the waveguide.

8 . The semiconductor package as claimed in claim 1 , further comprising a dummy die embedded in the integrated interconnect structure.

9 . The semiconductor package as claimed in claim 1 , wherein the photonic die is optically coupled to an optical device through the waveguide.

10 . The semiconductor package as claimed in claim 1 , wherein the integrated circuit package comprises a processing die and a memory die bonded over an interposer, and an encapsulating material laterally encapsulating the processing die and the memory die.

11 . A semiconductor package, comprising:
a package substrate; an integrated interconnect structure comprising an insulation body and a plurality of through vias extending through the insulation body; an interconnect device embedded in the integrated interconnect structure; an optical engine module bonded to the integrated interconnect structure and comprising an electronic die, a photonic die and a waveguide; an integrated circuit package bonded over the integrated interconnect structure and electrically coupled to the optical engine module through the interconnect device.

12 . The semiconductor package as claimed in claim 11 , wherein the waveguide is embedded in the integrated interconnect structure.

13 . The semiconductor package as claimed in claim 12 , wherein the electronic die is disposed over and connected to the interconnect device, and the photonic die is stacked over the electronic die and the waveguide.

14 . The semiconductor package as claimed in claim 11 , wherein the optical engine module is disposed over the integrated interconnect structure.

15 . The semiconductor package as claimed in claim 14 , wherein the waveguide and the electronic die are bonded to an upper surface of the integrated interconnect structure, and the photonic die is stacked over and coupled to the electronic die and the waveguide.

16 . The semiconductor package as claimed in claim 11 , wherein the integrated circuit package comprises a processing die and a memory die bonded over an interposer, and an encapsulating material laterally encapsulating the processing die and the memory die.

17 . A manufacturing method of a semiconductor package, comprising:
providing a plurality of through vias and an embedded device over a carrier; providing an insulation body over the carrier to form an integrated interconnect structure, wherein the insulation body at least laterally encapsulates the plurality of through vias and the embedded device; removing the carrier; bonding the integrated interconnect structure over a package substrate; bonding a photonic die over the integrated interconnect structure, wherein the photonic die is coupled to the embedded device; and bonding an integrated circuit package over the integrated interconnect structure, wherein the integrated circuit package is coupled to the photonic die through the photonic die.

18 . The manufacturing method of the semiconductor package as claimed in claim 17 , further comprising:
forming a concave on an outer edge of the insulation body; and disposed a waveguide in the concave before the photonic die is bonded over the integrated interconnect structure.

19 . The manufacturing method of the semiconductor package as claimed in claim 17 , further comprising:
bonding an electronic die over the integrated interconnect structure, wherein the photonic die is stacked over the electronic die, and the embedded device comprises an interconnect device electrically coupled to the electronic die and the integrated circuit package.

20 . The manufacturing method of the semiconductor package as claimed in claim 17 , wherein the embedded device comprises an electronic die, wherein the photonic die is stacked over and electrically coupled to the electronic die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiu Chao-Wei
• Hsieh Ching-Hua
• Lin Hsiu-Jen
• Pei Hao-Jan
• Cheng Chia-Shen
• Kuo Hsuan-Ting

Classifications

• H10W90/794

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/00 Primary

  Package configurations · CPC title