Seal ring structures

Patent metadata

Field	Value
Publication number	US-2025183199-A1
Application number	US-202519024075-A
Country	US
Kind code	A1
Filing date	Jan 16, 2025
Priority date	Dec 20, 2021
Publication date	Jun 5, 2025
Grant date	—

Abstract

Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a circuit region and a seal ring region surrounding the circuit region. The seal ring region includes a fin-shape structure in a form of a continuous ring, a first gate structure disposed on the fin-shape structure, and a second gate structure disposed on the fin-shape structure. The first gate structure is spaced apart from the second gate structure.

First claim

What is claimed is:

1 . An integrated circuit (IC) chip, comprising:
a circuit region; and a seal ring region surrounding the circuit region, the seal ring region comprising:
a fin-shape structure in a form of a continuous ring,
a first gate structure disposed on the fin-shape structure, and
a second gate structure disposed on the fin-shape structure, wherein the first gate structure is spaced apart from the second gate structure.

2 . The IC chip of claim 1 , wherein a lengthwise direction of the first gate structure is generally parallel to a lengthwise direction of the second gate structure.

3 . The IC chip of claim 1 , wherein a lengthwise direction of the first gate structure is generally perpendicular to a lengthwise direction of the second gate structure.

4 . The IC chip of claim 1 , wherein the first gate structure is located in a corner stress release (CSR) area of the IC chip, in the CSR area a lengthwise direction of the fin-shape structure forms a titled angle with respect to a lengthwise direction of the first gate structure.

5 . The IC chip of claim 4 , wherein the titled angle is non-orthogonal.

6 . The IC chip of claim 4 , wherein the titled angle is about 45 degrees.

7 . The IC chip of claim 1 , wherein each of the first and second gate structures has a contour of a top surface in its entirety located within a contour of a top surface of the fin-shape structure in a top view of the IC chip.

8 . The IC chip of claim 1 , wherein the circuit region comprises:
an active region, and a third gate structure across the active region, wherein a lengthwise direction of one of the first and second gate structures is non-parallel to a lengthwise direction of the third gate structure.

9 . The IC chip of claim 8 , wherein the active region is fully surrounded by the continuous ring.

10 . The IC chip of claim 8 , wherein the first and second gate structures have a same gate width that is wider than that of the third gate structure.

11 . An integrated circuit (IC) chip, comprising:
a fin-shape structure protruding from a first region of a substrate; a first gate structure disposed on a top surface of the fin-shape structure, wherein, in a top view of the IC chip, a contour of a top surface of the first gate structure is fully within a contour of a top surface of the fin-shape structure; a plurality of nanostructures vertically suspended above a second region of the substrate; and a second gate structure wrapping around each of the nanostructures.

12 . The IC chip of claim 11 , wherein the first region is located in a seal ring region of the IC chip, and the second region is located in an active circuit region of the IC chip.

13 . The IC chip of claim 11 , wherein the fin-shape structure includes first semiconductor layers and second semiconductor layers vertically interleaved with each other.

14 . The IC chip of claim 13 , wherein the first semiconductor layers and the nanostructures include a same material composition.

15 . The IC chip of claim 11 , wherein a lengthwise direction of the first gate structure forms a non-orthogonal angle with respective to a lengthwise direction of the fin-shape structure.

16 . A semiconductor structure, comprising:
a fin-shape structure having first semiconductor layers and second semiconductor layers vertically interleaved with each other; a first epitaxial feature; a second epitaxial feature, wherein the first and second epitaxial features sandwich the fin- shape structure; and a gate structure disposed on a top surface of the fin-shape structure, wherein the fin-shape structure extends lengthwise in a first direction, the gate structure extends lengthwise in a second direction that is different from the first direction, the first and second directions form a tilted angle that is non-orthogonal.

17 . The semiconductor structure of claim 16 , wherein the semiconductor structure is located in a corner stress release (CSR) region of an integrated circuit (IC) chip.

18 . The semiconductor structure of claim 16 , wherein the second epitaxial feature has a larger width than the first epitaxial feature.

19 . The semiconductor structure of claim 16 , wherein the gate structure is a first gate structure, the semiconductor structure further comprising:
a second gate structure disposed on the top surface of the fin-shape structure, wherein the second gate structure extends lengthwise in a third direction that is different from the second direction.

20 . The semiconductor structure of claim 16 , wherein the fin-shape structure forms a closed ring in a top view of the semiconductor structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Yu-Bey
• Peng Yuan-Ching
• Chang Yung Feng
• Lai Yen
• Kuo Jiun-Ming

Classifications

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title