Method of making semiconductor device having a contact structure

Patent metadata

Field	Value
Publication number	US-2025183161-A1
Application number	US-202519052715-A
Country	US
Kind code	A1
Filing date	Feb 13, 2025
Priority date	Feb 26, 2021
Publication date	Jun 5, 2025
Grant date	—

Abstract

A method of making semiconductor device includes forming an insulating layer. The method further includes patterning the insulating layer to define a via opening and a conductive line opening. The method further includes forming a via in the via opening. The method further includes forming a conductive line in the conductive line opening. Forming the conductive line includes forming a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and forming a conductive fill, wherein the first liner layer surrounds the conductive fill.

First claim

What is claimed is:

1 . A method of making semiconductor device, the method comprising:
forming an insulating layer; patterning the insulating layer to define a via opening and a conductive line opening; forming a via in the via opening; and forming a conductive line in the conductive line opening, wherein forming the conductive line comprises:
forming a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and
forming a conductive fill, wherein the first liner layer surrounds the conductive fill.

2 . The method of claim 1 , wherein forming the via comprises forming the via simultaneously with forming the conductive line.

3 . The method of claim 1 , wherein forming the via comprises forming the via over a portion of the first liner layer.

4 . The method of claim 1 , wherein forming the conductive line comprises forming a plurality of liner layers, the plurality of liner layers includes the first liner layer, and each of the plurality of liner layers is between the conductive fill and the insulating layer.

5 . The method of claim 1 , wherein forming the conductive fill comprises forming the conductive fill in direct contact with the via.

6 . The method of claim 1 , wherein forming the first liner layer comprises forming the first liner layer having a thickness along sidewalls of the conductive fill ranging from 8 angstroms to 20 angstroms.

7 . The method of claim 1 , wherein forming the first liner layer comprises forming the first liner layer in the via opening and the conductive line opening.

8 . A method of making a semiconductor device, the method comprising:
forming an insulating layer; patterning the insulating layer to define a via opening and a conductive line opening; forming a via in the via opening, wherein the via comprises a first conductive material; and forming a conductive line in the conductive line opening, wherein forming the conductive line comprises:
forming a first liner layer having a variable thickness, wherein thickness is measured in a direction perpendicular to a top surface of the insulating layer,
forming a second liner layer over the first liner layer, and
forming a conductive fill comprising a second conductive material, wherein the first liner layer, in a direction perpendicular to a top surface of the insulating layer, is between a portion of the insulating layer and the conductive fill.

9 . The method of claim 8 , wherein forming the second liner layer comprises forming the second liner layer having a variable thickness.

10 . The method of claim 8 , wherein the second conductive material is a same material as the first conductive material.

11 . The method of claim 8 , wherein forming the first liner layer comprises forming the first liner layer in the via opening.

12 . The method of claim 8 , wherein forming the second liner layer comprises forming the second liner layer in the via opening.

13 . The method of claim 8 , wherein patterning the insulating layer comprises defining the via opening having a tapered shape.

14 . The method of claim 8 , wherein patterning the insulating layer comprises defining the conductive line opening having a tapered shape.

15 . A method of making a semiconductor device, the method comprising:
forming an insulating layer; patterning the insulating layer to define a via opening and a conductive line opening; forming a via in the via opening, wherein the via comprises a first conductive material; and forming a conductive line in the conductive line opening, wherein forming the conductive line comprises:
forming a first liner layer having a variable thickness, wherein a portion of the first liner layer over the insulating layer has a uniform thickness, and
forming a conductive fill.

16 . The method of claim 15 , wherein forming the conductive fill comprises forming the conductive fill separated from the insulating layer by the first liner layer.

17 . The method of claim 15 , wherein forming the first liner layer comprises forming the first liner layer having a second thickness in the via opening.

18 . The method of claim 17 , wherein the second thickness is less than a thickness of the portion of the first liner layer over the insulating layer.

19 . The method of claim 15 , wherein forming the via comprises forming the via simultaneously with forming the conductive fill.

20 . The method of claim 15 , further comprising forming a second liner layer over a top-most surface of the conductive fill.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chin Shu-Cheng
• Liu Yao-Min
• Su Hung-Wen
• Chi Chih-Chien
• Lin Chi-Feng

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/084 Primary

  for dual-damascene structures · CPC title