Reconfigurable channel interfaces for memory devices

Patent metadata

Field	Value
Publication number	US-2025181537-A1
Application number	US-202519049984-A
Country	US
Kind code	A1
Filing date	Feb 10, 2025
Priority date	May 31, 2019
Publication date	Jun 5, 2025
Grant date	—

Abstract

Methods, systems, and devices for reconfigurable channel interfaces for memory devices are described. A memory device may be split into multiple logical channels, where each logical channel is associated with a memory array and a command/address (CA) interface. In some cases, the memory device may configure a first CA interface associated with a first channel to forward commands to a first memory array associated with the first channel and a second memory array associated with a second channel. The configuring may include isolating a second CA interface associated with the second channel from the second array and coupling the first CA interface with the second memory array.

First claim

What is claimed is:

1 . A method, comprising:
receiving, at a first command/address (CA) interface, a command indicating a configuration of a plurality of CA interfaces including the first CA interface, wherein each CA interface of the plurality of CA interfaces is coupled with a respective memory array of a plurality of memory arrays; deactivating a second CA interface of the plurality of CA interfaces from a second memory array of the plurality of memory arrays such that the second CA interface is isolated based at least in part on receiving the command; and coupling the first CA interface with the second memory array based at least in part on deactivating the second CA interface.

2 . The method of claim 1 , further comprising:
receiving, at the first CA interface based at least in part on coupling the first CA interface with the second memory array, a write command for the second memory array; and writing data to the second memory array based at least in part on the write command.

3 . The method of claim 2 , wherein deactivating the second CA interface comprises:
deactivating a clock associated with the second CA interface based at least in part on receiving the command.

4 . The method of claim 1 , further comprising:
receiving, at the first CA interface based at least in part on coupling the first CA interface with the second memory array, a read command for the second memory array; and retrieving data from the second memory array based at least in part on receiving the read command.

5 . The method of claim 4 , further comprising:
retrieving additional data from a first memory array of the plurality of memory arrays based at least in part on receiving the read command.

6 . The method of claim 5 , further comprising:
forwarding the read command from the first CA interface to the first memory array and the second memory array, wherein retrieving the data and the additional data is based at least in part on forwarding the read command.

7 . The method of claim 1 , further comprising:
receiving, at the first CA interface, a second command for associating the second CA interface with the second memory array; deactivating the first CA interface from the second memory array based at least in part on receiving the second command; and coupling the second CA interface with the second memory array based at least in part on deactivating the first CA interface.

8 . The method of claim 7 , further comprising:
activating the second CA interface based at least in part on receiving the second command.

9 . The method of claim 1 , wherein the command is received after a memory device comprising the first CA interface has performed a boot-up process.

10 . The method of claim 1 , wherein the command is received over one or more dedicated pins of the first CA interface as part of a boot-up process for a memory device comprising the first CA interface.

11 . An apparatus, comprising:
a first command/address (CA) interface coupled with a first control channel and associated with a first memory array; a second CA interface coupled with a second control channel and associated with a second memory array; and a selection component coupled with the first CA interface and the second CA interface and configured to selectively couple the second memory array with the first CA interface at a first time and to selectively couple the second memory array with the second CA interface at a second time, wherein the first CA interface is coupled with the first memory array at the first time and the second time.

12 . The apparatus of claim 11 , wherein:
commands for the second memory array are received over the first control channel based at least in part on the second memory array being coupled with the first CA interface.

13 . The apparatus of claim 11 , further comprising:
a third CA interface associated with a third memory array; and a fourth CA interface associated with a fourth memory array, wherein the selection component is coupled with the third CA interface and the fourth CA interface.

14 . The apparatus of claim 13 , wherein the first CA interface is coupled with the first memory array, the second memory array, the third memory array, and the fourth memory array using the selection component.

15 . The apparatus of claim 13 , wherein the selection component is further configured to couple the fourth memory array with the third CA interface or the fourth CA interface.

16 . The apparatus of claim 13 , wherein the selection component is further configured to couple the third memory array with the first CA interface or the third CA interface and to couple the fourth memory array with the first CA interface or the fourth CA interface.

17 . The apparatus of claim 13 , wherein the first memory array, the second memory array, the third memory array, and the fourth memory array or a combination thereof comprise volatile memory cells.

18 . The apparatus of claim 11 , wherein the selection component comprises a multiplexer coupled with the first CA interface and the second CA interface.

19 . The apparatus of claim 18 , wherein the selection component further comprises a latching component configured to transmit a selection signal to the multiplexer.

20 . A method, comprising:
receiving a read command at a command/address (CA) interface, a first memory array and a second memory array, the first memory array coupled with a first data channel and the second memory array coupled with a second data channel different than the first data channel; retrieving, based at least in part on identifying that the read command is for the second memory array, a set of data from the second memory array based at least in part on receiving the read command; and transmitting the set of data over the second data channel based at least in part on retrieving the set of data from the second memory array.

Assignees

• Lodestar Licensing Group Llc

Inventors

• Richter Michael Dieter

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C11/4096 Primary

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title