Transistor device having semiconductor spacer, and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2025169186-A1
Application number	US-202418642910-A
Country	US
Kind code	A1
Filing date	Apr 23, 2024
Priority date	Nov 22, 2023
Publication date	May 22, 2025
Grant date	—

Abstract

Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes a semiconductor spacer between the upper transistor and the lower transistor. Related methods of forming transistor devices are also provided.

First claim

What is claimed is:

1 . A transistor device comprising:
a substrate; a transistor stack on the substrate, wherein the transistor stack comprises a lower transistor and an upper transistor that is on top of the lower transistor; and a semiconductor spacer between the upper transistor and the lower transistor.

2 . The transistor device of claim 1 ,
wherein the upper transistor and the lower transistor each comprise semiconductor channel layers, and wherein the semiconductor spacer is thicker, in a vertical direction, than each of the semiconductor channel layers.

3 . The transistor device of claim 2 , further comprising a bottom isolation region that is between the substrate and the semiconductor channel layers of the lower transistor.

4 . The transistor device of claim 3 , wherein the bottom isolation region is thinner, in the vertical direction, than the semiconductor spacer.

5 . The transistor device of claim 3 , wherein the bottom isolation region comprises silicon nitride.

6 . The transistor device of claim 2 , wherein the semiconductor spacer has a width, in a lateral direction, that is equal to a width of each of the semiconductor channel layers.

7 . The transistor device of claim 2 , wherein the semiconductor spacer and the semiconductor channel layers comprise the same semiconductor material.

8 . The transistor device of claim 7 , wherein the semiconductor material comprises crystalline silicon.

9 . The transistor device of claim 7 , wherein the semiconductor material is free of germanium, free of carbon, free of nitrogen, and free of oxygen.

10 . The transistor device of claim 2 , further comprising:
a source/drain (S/D) isolation region that is on a sidewall of the semiconductor spacer; and an upper S/D region that is on the S/D isolation region and electrically connected to the semiconductor channel layers of the upper transistor, wherein the S/D isolation region is thicker, in the vertical direction, than the semiconductor spacer.

11 . The transistor device of claim 10 , further comprising a lower S/D region that is electrically connected to the semiconductor channel layers of the lower transistor,
wherein the S/D isolation region separates the lower S/D region from the upper S/D region.

12 . The transistor device of claim 11 , further comprising:
a gate between the semiconductor channel layers of the upper transistor; and an insulating spacer on a sidewall of the gate, wherein an uppermost surface of the semiconductor spacer contacts a lowermost surface of the insulating spacer, and wherein an upper portion of the S/D isolation region overlaps, in a lateral direction, the sidewall of the gate and a sidewall of the insulating spacer.

13 . The transistor device of claim 12 ,
wherein the insulating spacer comprises silicon nitride, and wherein the semiconductor channel layers comprise nanosheets.

14 . A transistor device comprising:
a substrate; a transistor stack on the substrate, wherein the transistor stack comprises a lower transistor and an upper transistor that is on top of the lower transistor, and wherein the upper transistor and the lower transistor each comprise semiconductor channel layers; a silicon spacer that separates the upper transistor from the lower transistor, wherein the silicon spacer is free of nitrogen; and a bottom isolation region that is between the substrate and the semiconductor channel layers of the lower transistor.

15 . The transistor device of claim 14 , further comprising:
a source/drain (S/D) isolation region that is on a sidewall of the silicon spacer; an upper S/D region that is on the S/D isolation region and electrically connected to the semiconductor channel layers of the upper transistor; and a lower S/D region that is electrically connected to the semiconductor channel layers of the lower transistor, wherein the S/D isolation region separates the lower S/D region from the upper S/D region, and wherein the S/D isolation region is thicker, in a vertical direction, than the silicon spacer.

16 . The transistor device of claim 15 ,
wherein the S/D isolation region comprises an oxide, and wherein the bottom isolation region comprises silicon nitride and is thinner, in the vertical direction, than the silicon spacer.

17 . A method of forming a transistor device, the method comprising:
forming a stack of semiconductor layers that alternate with sacrificial gate layers on a substrate, wherein another sacrificial layer is between the substrate and a lowermost one of the sacrificial gate layers; and replacing the other sacrificial layer with a bottom isolation region, wherein upper ones of the semiconductor layers comprise upper channel layers of an upper transistor, wherein lower ones of the semiconductor layers comprise lower channel layers of a lower transistor, and wherein a middle one of the semiconductor layers separates the upper channel layers from the lower channel layers and is thicker, in a vertical direction, than each of the upper channel layers and each of the lower channel layers.

18 . The method of claim 17 , further comprising:
forming a lower source/drain (S/D) region on sidewalls of the lower channel layers; forming an S/D isolation region on the lower S/D region and on a sidewall of the middle one of the semiconductor layers; and forming an upper S/D region on the S/D isolation region and on sidewalls of the upper channel layers.

19 . The method of claim 18 , wherein forming the lower S/D region comprises forming the lower S/D region on a sidewall of the bottom isolation region.

20 . The method of claim 18 , wherein forming the S/D isolation region comprises forming an uppermost surface of the S/D isolation region at a level higher, in the vertical direction, than an uppermost surface of the middle one of the semiconductor layers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• PARK Keumseok
• Yun Seungchan
• Seo Kang-Ill

Classifications

• H10D84/856

  the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D64/671

  the conductor having lateral variation in doping or structure · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title