Semiconductor memory device, method for fabricating the same and electronic system including the same

Patent metadata

Field	Value
Publication number	US-2025151272-A1
Application number	US-202418746736-A
Country	US
Kind code	A1
Filing date	Jun 18, 2024
Priority date	Nov 8, 2023
Publication date	May 8, 2025
Grant date	—

Abstract

Semiconductor memory devices including memory cells arranged three-dimensionally, methods for fabricating the same, and electronic systems including the same are provided. The semiconductor memory device includes a first stacked structure including first gate electrodes sequentially stacked and spaced apart from each other, a second stacked structure on the first stacked structure and including second gate electrodes sequentially stacked and spaced apart from each other, and a channel structure extending in a vertical direction and passing through the first and second stacked structures, wherein the channel structure includes a channel layer including a first pillar portion crossing the first gate electrodes, a second pillar portion crossing the second gate electrodes, and a horizontal portion extending along a plane crossing the vertical direction, the horizontal portion connecting the first and second pillar portions, and a data storage layer extending along an outer side of the channel layer.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a first stacked structure including a plurality of first gate electrodes sequentially stacked and spaced apart from each other; a second stacked structure on the first stacked structure, the second stacked structure including a plurality of second gate electrodes sequentially stacked and spaced apart from each other; and a channel structure extended in a vertical direction to pass through the first stacked structure and the second stacked structure, wherein the channel structure includes,
a channel layer including a first pillar portion crossing the plurality of first gate electrodes, a second pillar portion crossing the plurality of second gate electrodes, and a horizontal portion extended along a plane crossing the vertical direction, the horizontal portion connecting the first pillar portion and the second pillar portion, and
a data storage layer extending along an outer side of the channel layer.

2 . The semiconductor memory device of claim 1 , wherein
a width of the first pillar portion is reduced as the first pillar portion is directed toward the second stacked structure, and a width of the second pillar portion is reduced as the second pillar portion is directed toward the first stacked structure.

3 . The semiconductor memory device of claim 1 , wherein
the plurality of first gate electrodes are stacked on an upper surface of the second stacked structure in a stepwise shape, and the plurality of second gate electrodes are stacked on a lower surface of the first stacked structure in a stepwise shape.

4 . The semiconductor memory device of claim 1 , wherein
the first stacked structure includes a first stack and a second stack, the first stack and the second stack being sequentially stacked on the second stacked structure, each of the first stack and the second stack includes the plurality of first gate electrodes, and a width of the channel structure in the first stack is greater than a width of the channel structure in the second stack, at a boundary surface between the first stack and the second stack.

5 . The semiconductor memory device of claim 1 , wherein the channel structure further includes:
a first filling insulating layer at least partially filling an inside of the first pillar portion; and a second filling insulating layer at least partially filling an inside of the second pillar portion; and wherein the horizontal portion separates the first filling insulating layer from the second filling insulating layer.

6 . The semiconductor memory device of claim 5 , wherein the channel structure further includes:
a first channel pad connected to one end of the first pillar portion, on the first filling insulating layer; and a second channel pad connected to one end of the second pillar portion, on the second filling insulating layer.

7 . The semiconductor memory device of claim 1 , wherein the data storage layer includes:
a first dielectric layer including a first tunneling insulating layer, a first charge storage layer and a first blocking insulating layer that are sequentially stacked on an outer side of the first pillar portion; and a second dielectric layer including a second tunneling insulating layer, a second charge storage layer and a second blocking insulating layer that are sequentially stacked on an outer side of the second pillar portion, and wherein the second blocking insulating layer separates the first charge storage layer from the second charge storage layer.

8 . The semiconductor memory device of claim 1 , further comprising:
a pad insulating layer interposed between the first stacked structure and the second stacked structure, wherein the channel layer further includes a pad portion extended along a plane crossing the vertical direction in the pad insulating layer, a width of the pad portion is greater than a width of the first pillar portion, and the second pillar portion is connected to the pad portion.

9 . The semiconductor memory device of claim 1 , further comprising:
a source structure connected to the first pillar portion, on the first stacked structure; and a bit line connected to the second pillar portion, on the second stacked structure.

10 . The semiconductor memory device of claim 1 , further comprising:
a peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit element on the peripheral circuit substrate, wherein the second stacked structure is interposed between the first stacked structure and the peripheral circuit structure.

11 . A semiconductor memory device comprising:
a peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit element on the peripheral circuit substrate; a first stacked structure on the peripheral circuit structure, the first stacked structure including a plurality of first gate electrodes sequentially stacked and spaced apart from each other; a second stacked structure between the peripheral circuit structure and the first stacked structure, the second stacked structure including a plurality of second gate electrodes sequentially stacked and spaced apart from each other; a channel layer extending in a vertical direction and passing through the first stacked structure and the second stacked structure, the channel layer including a first semiconductor layer crossing the plurality of first gate electrodes and a second semiconductor layer crossing the plurality of second gate electrodes; a data storage layer including
a first dielectric layer interposed between the first stacked structure and the first semiconductor layer, and
a second dielectric layer interposed between the second stacked structure and the second semiconductor layer;
a source structure connected to the first semiconductor layer, on the first stacked structure; and a bit line connected to the second semiconductor layer and between the peripheral circuit structure and the second stacked structure, wherein a width of the first semiconductor layer is reduced as the first semiconductor layer is directed toward the second stacked structure, a width of the second semiconductor layer is reduced as the second semiconductor layer is directed toward the first stacked structure, and the second semiconductor layer includes a horizontal portion, the horizontal portion extending along a plane crossing the vertical direction and connected to the first semiconductor layer.

12 . The semiconductor memory device of claim 11 , wherein the horizontal portion is in the first stacked structure.

13 . The semiconductor memory device of claim 11 , further comprising:
a pad insulating layer interposed between the first stacked structure and the second stacked structure, wherein the first semiconductor layer includes a pad portion extending along a plane crossing the vertical direction in the pad insulating layer, a width of the pad portion is greater than a width of the second semiconductor layer at the plane, and the second semiconductor layer is connected to the pad portion.

14 . The semiconductor memory device of claim 11 , wherein each of the first semiconductor layer and the second semiconductor layer includes a polysilicon (poly-Si) layer.

15 . The semiconductor memory device of claim 11 , wherein each of the first dielectric layer and the second dielectric layer includes a tunneling insulating layer, a charge storage layer and a blocking insulating layer that are sequentially stacked on an outer side of the channel layer.

16 . The semiconductor memory

Assignees

• Samsung Electronics Co Ltd

Inventors

• Moon Joon
• Son Young Hwan
• Kang Shin Hwan
• Sung Suk Kang

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W90/00

  Package configurations · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title