Selective Dielectric Capping for Hybrid Bonding

US2025149474A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025149474-A1
Application numberUS-202418809472-A
CountryUS
Kind codeA1
Filing dateAug 20, 2024
Priority dateNov 3, 2023
Publication dateMay 8, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for increasing dielectric bonding strength during wafer-level processing is incorporated into a hybrid bonding process. A method may include immersing a substrate into a chemical bath at atmospheric conditions where the chemical bath forms a self-assembled monolayer on metal surfaces of the substrate and selectively depositing a high-k dielectric material to form a dielectric cap on dielectric surfaces of the substrate absent of the self-assembled monolayer.

First claim

Opening claim text (preview).

1 . A method for increasing dielectric bonding strength during wafer-level processing, comprising: immersing a substrate into a chemical bath, wherein the chemical bath forms a self-assembled monolayer on at least one metal surface of the substrate; and selectively depositing a dielectric material to form a dielectric cap on at least one dielectric surface of the substrate absent of the self-assembled monolayer. 2 . The method of claim 1 , wherein immersing the substrate into the chemical bath occurs at atmospheric pressure and ambient temperature. 3 . The method of claim 1 , further comprising: removing the self-assembled monolayer from the substrate; bonding the dielectric material of the substrate to another substrate with surfaces covered by the dielectric material by contacting substrates together; and annealing substrates to bond metal surfaces together. 4 . The method of claim 3 , further comprising: removing the self-assembled monolayer using a plasma-based process for approximately 10 seconds to approximately 60 seconds. 5 . The method of claim 3 , wherein the substrate is a die. 6 . The method of claim 3 , wherein annealing occurs at a temperature of approximately 150 degrees Celsius. 7 . The method of claim 1 , wherein the chemical bath includes an alkanethiol. 8 . The method of claim 7 , wherein the alkanethiol has a linear structure or a benzene ring structure. 9 . The method of claim 1 , wherein the dielectric material is a high-k dielectric material. 10 . The method of claim 9 , wherein the high-k dielectric material is aluminum oxide or hafnium oxide. 11 . The method of claim 1 , wherein the substrate is immersed in the chemical bath for approximately 10 minutes to approximately 30 minutes. 12 . The method of claim 1 , wherein the metal surface is copper, silver, gold, palladium, platinum, cobalt, titanium, nickel, or combinations thereof. 13 . The method of claim 1 , wherein a thickness of the dielectric material is greater than zero nm to approximately 10 nm. 14 . A method for increasing dielectric bonding strength during wafer-level processing, comprising: immersing a substrate into a chemical bath, wherein the chemical bath forms a self-assembled monolayer on at least one metal surface of the substrate and wherein immersing the substrate into the chemical bath occurs at atmospheric pressure and ambient temperature; and selectively depositing a high-k dielectric material to form a dielectric cap on at least one dielectric surface of the substrate absent of the self-assembled monolayer, wherein a thickness of the high-k dielectric material is greater than zero nm to approximately 10 nm. 15 . The method of claim 14 , wherein the substrate is immersed in the chemical bath for approximately 10 minutes to approximately 30 minutes. 16 . The method of claim 14 , further comprising: removing the self-assembled monolayer from the substrate; bonding the high-k dielectric material of the substrate to another substrate with surfaces covered by the high-k dielectric material by contacting substrates together; and annealing substrates to bond metal surfaces together. 17 . The method of claim 16 , further comprising: removing the self-assembled monolayer using a plasma-based process for approximately 10 seconds to approximately 60 seconds. 18 . The method of claim 14 , wherein the chemical bath includes an alkanethiol with a linear structure or a benzene ring structure. 19 . The method of claim 14 , wherein the high-k dielectric material is aluminum oxide or hafnium oxide. 20 . A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for increasing dielectric bonding strength during wafer-level processing to be performed, the method comprising: immersing a substrate into a chemical bath, wherein the chemical bath forms a self-assembled monolayer on at least one metal surface of the substrate and wherein immersing the substrate into the chemical bath occurs at atmospheric pressure and ambient temperature; and selectively depositing a dielectric material to form a dielectric cap on at least one dielectric surface of the substrate absent of the self-assembled monolayer.

Assignees

Inventors

Classifications

  • not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

  • comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

  • Structures or relative sizes of bond pads · CPC title

  • Bond pads having multiple stacked layers · CPC title

  • Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01951) · CPC title

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What does patent US2025149474A1 cover?
A method for increasing dielectric bonding strength during wafer-level processing is incorporated into a hybrid bonding process. A method may include immersing a substrate into a chemical bath at atmospheric conditions where the chemical bath forms a self-assembled monolayer on metal surfaces of the substrate and selectively depositing a high-k dielectric material to form a dielectric cap on di…
Who is the assignee on this patent?
Applied Materials Inc, Univ Nanyang Tech
What technology area does this patent fall under?
Primary CPC classification H10P14/69392. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu May 08 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).