Multiple register allocation sizes for gpu hardware threads

Patent metadata

Field	Value
Publication number	US-2025147762-A1
Application number	US-202318504407-A
Country	US
Kind code	A1
Filing date	Nov 8, 2023
Priority date	Nov 8, 2023
Publication date	May 8, 2025
Grant date	—

Abstract

Described herein is a graphics processor having processing resources with configurable thread and register configurations. Program code can configure a number of registers and accumulators that will be used by hardware threads during execution of the program code by the graphics processor. Processing resources within the graphics processor can be configured to assign different numbers of registers and accumulators to hardware threads based on the configuration requested by program code to be executed by the processing resource.

First claim

What is claimed is:

1 . A graphics processor comprising:
a memory interface; a processing cluster coupled with the memory interface, the processing cluster including a plurality of graphics cores coupled via a data interconnect; and circuitry to dispatch workloads for execution by processing resources within a graphics core of the plurality of graphics cores, the circuitry configured to:
receive a request to dispatch program code for execution, the program code associated with a register configuration selected from a plurality of register configurations;
select a processing resource of a plurality of processing resources within the graphics core, the processing resource determined to have sufficient available resources to satisfy the register configuration for the program code;
assign a number of registers to a hardware thread of the processing resource based on the register configuration selected for the program code; and
execute an instruction of the program code via the hardware thread.

2 . The graphics processor of claim 1 , wherein each of the plurality of register configurations specify a number of registers to assign to the hardware thread of the processing resource.

3 . The graphics processor of claim 2 , wherein the number of registers to assign to the hardware thread of the processing resource include a first number of general-purpose registers to assign to the hardware thread of the processing resource and a second number of accumulator registers to assign to the hardware thread of the processing resource.

4 . The graphics processor of claim 3 , wherein the register configuration is selected for the program code based on a shader type associated with the program code.

5 . The graphics processor of claim 1 , wherein the circuitry is configured to track a number of registers of the processing resource that are allocated to active hardware threads within the processing resource.

6 . The graphics processor of claim 5 , wherein the circuitry is configured to track a number of free registers in each respective processing resource of the plurality of processing resources within the graphics core.

7 . The graphics processor of claim 5 , wherein the circuitry is configured to track registers of the processing resource at register block granularity, wherein a register block includes multiple contiguous registers.

8 . The graphics processor of claim 7 , wherein a register block includes 32 registers.

9 . The graphics processor of claim 8 , wherein the circuitry is configured to select the processing resource of the plurality of processing resources within the graphics core via a round-robin scheduler.

10 . The graphics processor of claim 9 , wherein the circuitry is configured to:
determine, based on the register configuration associated with the program code, whether sufficient contiguous register blocks are available in the processing resource; bypass the processing resource in response to a determination that sufficient contiguous register blocks are not available; and select a next available processing resource in the plurality of processing resources.

11 . A method for comprising:
receiving a request to dispatch program code for execution to a processing resource within a graphics core of a graphics processor; determining whether variable registers per thread (VRT) is enabled for the program code; statically configuring the processing resource within the graphics core that was selected to execute the program code with a default number of registers per thread in response to a determination that VRT is not enabled for the program code; dynamically allocating registers to a hardware thread of the processing resource according to a register configuration associated with the program code in response to a determination that VRT is enabled for the program code; and executing an instruction of the program code via the hardware thread.

12 . The method of claim 11 , wherein the register configuration associated with the program code is selected from a plurality of register configurations, each of the plurality of register configurations specify a number of registers to assign to the hardware thread of the processing resource.

13 . The method of claim 12 , further comprising selecting a register configuration from the plurality of register configurations based on a shader type associated with the program code.

14 . The method of claim 11 , further comprising:
determining whether the program code is an asynchronous compute program; determining an asynchronous compute throttle limit configured for the processing resource; and dispatching the hardware thread of the program code in response to a determination that the asynchronous compute throttle limit has not been reached.

15 . The method of claim 14 , further comprising, in response to the determination that VRT is enabled for the program code:
scaling the asynchronous compute throttle limit based on the register configuration; and stalling dispatch of the hardware thread to the processing resource based on a scaled asynchronous compute throttle limit.

16 . A graphics processing system comprising:
a memory interface; a processing cluster coupled with the memory interface, the processing cluster including a plurality of graphics cores coupled via a data interconnect; and circuitry to dispatch workloads for execution by processing resources within a graphics core of the plurality of graphics cores, the circuitry configured to:
receive a request to dispatch program code for execution, the program code associated with a register configuration selected from a plurality of register configurations;
select a processing resource of a plurality of processing resources within the graphics core, the processing resource determined to have sufficient available resources to satisfy the register configuration for the program code;
assign a number of registers to a hardware thread of the processing resource based on the register configuration selected for the program code; and
execute an instruction of the program code via the hardware thread.

17 . The graphics processing system of claim 16 , wherein each of the plurality of register configurations specify a number of registers to assign to the hardware thread of the processing resource.

18 . The graphics processing system of claim 17 , wherein the number of registers to assign to the hardware thread of the processing resource include a first number of general-purpose registers to assign to the hardware thread of the processing resource and a second number of accumulator registers to assign to the hardware thread of the processing resource.

19 . The graphics processing system of claim 18 , wherein the register configuration is selected for the program code based on a shader type associated with the program code.

20 . The graphics processing system of claim 16 , wherein the circuitry is configured to track a number of registers of the processing resource that are allocated to active hardware threads within the processing resource.

Assignees

• Intel Corp

Inventors

• Ranganathan Vasanth
• Chen Gang
• Pal Supratim
• Parra Osorio Jorge Eduardo
• Hunter Arthur
• Kuznetsov Boris
• N K Deepak
• Seemakurthi Siva Kumar
• Valerio James
• Chavan Shubham Dinesh
• Kumar Singh Abhishek
• Pandya Samir
• Tippannanavar Niranjan Sandeep
• Curtis Alan
• Philip Jain
• Kulkarni Maltesh
• Fu Fangwen
• Wiegert John
• Schwartz Brent

Classifications

• G06T15/005

  General purpose rendering architectures · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F9/30134 Primary

  Register stacks; shift registers · CPC title