Method for optimizing photomask

US2025147411A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025147411-A1
Application numberUS-202318501615-A
CountryUS
Kind codeA1
Filing dateNov 3, 2023
Priority dateNov 3, 2023
Publication dateMay 8, 2025
Grant date

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  1. Title

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method includes receiving a layout; performing an optimization process to the layout to generate an optimized layout, wherein the optimization process comprising simulating a mask image of a photomask based on the layout; simulating an aerial image projected on a photoresist layer based on the mask image; simulating a resist image of the photoresist layer based on the aerial image; simulating an etch image of a layer underneath the photoresist layer based on the resist image; and performing an inverse lithographic technology (ILT) process to generate the optimized layout, wherein the ILT process is performed based on the mask image, the aerial image, the resist image, and the etch image; and fabricating a photomask based on the optimized layout.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method, comprising: receiving a layout; performing an optimization process to the layout to generate an optimized layout, wherein the optimization process comprising: simulating a mask image of a photomask based on the layout; simulating an aerial image projected on a photoresist layer based on the mask image; simulating a resist image of the photoresist layer based on the aerial image; simulating an etch image of a layer underneath the photoresist layer based on the resist image; and performing an inverse lithographic technology (ILT) process to generate the optimized layout, wherein the ILT process is performed based on the mask image, the aerial image, the resist image, and the etch image; and fabricating a photomask based on the optimized layout. 2 . The method of claim 1 , wherein the ILT process comprises performing an iterative process to the layout using a function defined as: w 1 ← w 0 - η ⁢ dL dw ❘ "\[RightBracketingBar]" w = w 0 ⁢ w * = arg ⁢ min ⁢ L ⁡ ( w ) wherein w is a variable of the layout; w 0 , w 1 , and w* are layouts at different stages of the iterative process; η is a learning rate; and L(w) is a loss function, and L(w) is defined as a difference between the simulated etch image and the layout. 3 . The method of claim 2 , wherein the function is further expressed as: w 1 ← w 0 - η ⁢ dL dEI * dEI dRI * dRI dAI * dAI dMI * dMI dw ❘ "\[RightBracketingBar]" EI = EI 0 , RI = RI 0 , AI = AI 0 , MI = MI 0 , w = w 0 ⁢ w * = arg ⁢ min ⁢ L ⁡ ( w ) wherein EI is the simulated etch image; RI is the simulated resist image; AI is the simulated aerial image; and MI is the simulated mask image. 4 . The method of claim 1 , wherein: a pattern of the layout comprising a first feature; a pattern of the photomask comprising a second feature and a first assisting feature, wherein the second feature corresponds to the first feature of the pattern of the layout, while the pattern of the layout has no feature corresponding to the first assisting feature. 5 . The method of claim 4 , further comprising patterning the photoresist layer using the photomask, such that the pattern of the photomask is transferred to the photoresist layer, wherein a pattern of the photoresist layer comprises a third feature and a second assisting feature, wherein the third feature corresponds to the second feature of the pattern of the photomask, and the second assisting feature corresponds to the first assisting feature of the pattern of the photomask. 6 . The method of claim 5 , further comprising patterning a layer using the photoresist layer, such that the pattern of the photoresist layer is transferred to the layer, wherein a pattern of the layer comprises a fourth feature, wherein the fourth feature corresponds to the third feature of the pattern of the photoresist layer, while the pattern of the layer has no feature corresponding to the second assisting feature of the pattern of the photoresist layer. 7 . The method of claim 1 , wherein simulating the resist image of the photoresist layer is performed using a machine-learning based module, and the machine-learning based module is trained based on a database of aerial image data and resist image data. 8 . The method of claim 1 , wherein simulating the etch image of the layer is performed using a machine-learning based module, and the machine-learning based module is trained based on a database of resist image data and etch image data. 9 . A method, comprising: receiving a layout; performing a first optimization process to the layout to generate a first optimized layout; transferring the fi

Assignees

Inventors

Classifications

  • Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

  • Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes · CPC title

  • G03F1/82Primary

    Auxiliary processes, e.g. cleaning or inspecting · CPC title

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What does patent US2025147411A1 cover?
A method includes receiving a layout; performing an optimization process to the layout to generate an optimized layout, wherein the optimization process comprising simulating a mask image of a photomask based on the layout; simulating an aerial image projected on a photoresist layer based on the mask image; simulating a resist image of the photoresist layer based on the aerial image; simulating…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification G03F1/82. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu May 08 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).