System and method of generating signals for analog-digital converter (adc) calibration

Patent metadata

Field	Value
Publication number	US-2025141466-A1
Application number	US-202318498321-A
Country	US
Kind code	A1
Filing date	Oct 31, 2023
Priority date	Oct 31, 2023
Publication date	May 1, 2025
Grant date	—

Abstract

A device may include an oscillator and a driver. The oscillator may be coupled to circuitry providing calibration of the oscillator. The oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicating an amplitude to apply to the second signal. The driver may provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

First claim

What is claimed is:

1 . A device comprising:
an oscillator coupled to circuitry providing calibration of the oscillator, the oscillator configured to receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC); and a driver coupled to the oscillator and the ADC, the driver configured to:
receive the second signal from the oscillator;
receive a third signal indicating an amplitude to apply to the second signal; and
provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

2 . The device of claim 1 , wherein the second signal is a pair of signals that are 180 degrees out of phase with each other.

3 . The device of claim 1 , wherein the driver is configured to:
receive a fourth signal indicating a rise time and a fall time to apply to the second signal; and provide, to the ADC based at least on the second signal, the third signal and the fourth signal, an output signal having the first frequency, the amplitude, the rise time, and the fall time.

4 . The device of claim 1 , wherein the driver comprises:
one or more amplifiers coupled to the oscillator and configured to amplify the second signal based at least on the third signal to generate the output signal.

5 . The device of claim 4 , wherein the driver comprises:
one or more capacitors coupled to an output of the one or more amplifier, wherein the driver is configured to provide, to the ADC, the output signal through the one or more capacitors.

6 . The device of claim 4 , wherein the driver comprises:
one or more switches coupled to an output of the one or more amplifiers, wherein the driver is further configured to
receive a fifth signal indicating to enable or disable the driver such that the driver is enabled during the calibration of the ADC and is disabled responsive to the ADC being calibrated, and
turn on or turn off the one or more switches according to the fifth signal.

7 . The device of claim 1 , wherein
the ADC receives one or more input signals through a first amplifier, and the driver is configured to turn off the first amplifier during the calibration of the ADC and turn on the first amplifier responsive to the ADC being calibrated.

8 . The device of claim 7 , wherein the driver is configured to:
provide, to the first amplifier, a sixth signal indicating to enable or disable the first amplifier such that the first amplifier is disabled during the calibration of the ADC and is enabled responsive to the ADC being calibrated, and turn on or turn off the first amplifier according to the sixth signal.

9 . The device of claim 7 , wherein during the calibration of the ADC,
the driver is configured to provide the output signal to a second amplifier that has impedance smaller than the impedance of the first amplifier, and the ADC receives the one or more input signals from the second amplifier.

10 . Circuitry comprising:
a first circuit coupled to an oscillator and configured to:
receive a signal indicating a first frequency to be used for calibration of an analog-to-digital converter (ADC),
calibrate a frequency of the oscillator, and
generate, based at least on the signal and the frequency of the oscillator, one or more first signals; and
a second circuit coupled to the oscillator and configured to:
receive, from the first circuit, the one or more first signals, and
control, based at least on the one or more first signals, the oscillator to generate a second signal having the first frequency.

11 . The circuitry of claim 10 , wherein the first circuit comprises:
a controller; a first counter configured to receive a first clock signal outputted from the oscillator; and a second counter configured to receive a second clock signal.

12 . The circuitry of claim 11 , wherein the controller is a circuit implementing a finite-state machine (FSM).

13 . The circuitry of claim 11 , wherein the controller is configured to:
receive the signal indicating a first quantity corresponding to the first frequency; receive a third signal indicating to start calibrating the oscillator; in response to the third signal, reset the first counter and the second counter, control each of the first counter and the second counter to start counting, and determine whether a counter number indicated by an output of the second counter is equal to a second quantity; in response to determining that the counter number of the second counter is equal to the second quantity, control the first counter to stop counting and determine whether a counter number indicated by an output of the first counter is equal to the first quantity; and in response to determining that the counter number of the first counter is not equal to the first quantity, generate the one or more first signals.

14 . The circuitry of claim 13 , wherein the controller is configured to:
in response to determining that the counter number of the first counter is equal to the first quantity, disable the first counter and the second counter.

15 . The circuitry of claim 11 , wherein the controller is configured to:
receive a fifth signal indicating to enable or disable the first circuit such that the first circuit is enabled during the calibration of the ADC and is disabled responsive to the ADC being calibrated.

16 . The circuitry of claim 10 , wherein
the oscillator is a ring oscillator, the ring oscillator comprises a plurality of amplifiers, the one or more first signals comprises a first control signal and a second control signal, and the second circuit is configured to:
determine a first number of amplifiers, among the plurality of amplifiers, according to the first control signal; and
enable the first number of amplifiers, among the plurality of amplifiers.

17 . The circuitry of claim 16 , wherein the second circuit is configured to:
determine a second number of capacitors according to the second control signal, and connect the second number of capacitors to respective amplifiers, among the plurality of amplifies.

18 . The circuitry of claim 10 , wherein the second circuit is configured to:
receive a sixth signal indicating to enable or disable the oscillator such that the oscillator is enabled during the calibration of the ADC and is disabled responsive to the ADC being calibrated; and enable or disable the oscillator according to the sixth signal.

19 . A method comprising:
receiving, by a first circuit coupled to an oscillator, a signal indicating a first frequency to be used for calibration of an analog-to-digital converter (ADC); calibrating, by the first circuit, a frequency of the oscillator; generating, by the first circuit based at least on the signal and the frequency of the oscillator, one or more first signals; receiving, by a second circuit coupled to the oscillator, from the first circuit, the one or more first signals; and controlling, by the second circuit based at least on the one or more first signals, the oscillator to generate a second signal having the first frequency.

20 . The method of claim 19 , further comprising:
receiving, by the second circuit, a further signal indicating to enable or disable the oscillator such that the oscillator is enabled during the calibration of the ADC and is disabled responsive to the ADC being calibrated; and enabling or disabling, by the

Assignees

• Avago Tech Int Sales Pte Lid

Inventors

• Liu Yong
• Yang Xi
• Yang Xiaochen
• Cao Jun

Classifications

• H03M1/508 Primary

  the pulse width modulator being of the self-oscillating type · CPC title

• H03M1/1014

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/10

  Calibration or testing · CPC title