Erasing memory

Patent metadata

Field	Value
Publication number	US-2025140324-A1
Application number	US-202519010407-A
Country	US
Kind code	A1
Filing date	Jan 6, 2025
Priority date	Aug 29, 2019
Publication date	May 1, 2025
Grant date	—

Abstract

Memories having a controller configured to increase a voltage level applied to a data line and decrease a voltage level applied to a control gate of a transistor connected between the data line and a string of series-connected memory cells during a first period of time, increase the voltage level applied to the data line and increase the voltage level applied to the control gate of the transistor at a same rate in response to an end of the first period of time, and ceasing increasing the voltage level applied to the data line and ceasing increasing the voltage level applied to the control gate of the transistor in response to the voltage level applied to the data line reaching a predetermined voltage level.

First claim

What is claimed is:

1 . A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; a plurality of data lines, wherein each data line of the plurality of data lines is selectively connected to a respective subset of strings of series-connected memory cells of the plurality of strings of series-connected memory cells; a common source selectively connected to each string of series-connected memory cells of the plurality of strings of series-connected memory cells; and a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
increase a voltage level applied to a data line of the plurality of data lines during a first period of time;
decrease a voltage level applied to a control gate of a transistor connected between the data line and a string of series-connected memory cells of its respective subset of strings of series-connected memory cells during the first period of time;
in response to an end of the first period of time, increase the voltage level applied to the data line and increase the voltage level applied to the control gate of the transistor at a same rate; and
in response to the voltage level applied to the data line reaching a predetermined voltage level, ceasing increasing the voltage level applied to the data line and ceasing increasing the voltage level applied to the control gate of the transistor.

2 . The memory of claim 1 , wherein the controller is further configured to cause the memory to:
while the voltage level applied to the data line is at the predetermined voltage level, apply a voltage level to a control gate of a memory cell of the string of series-connected memory cells expected to remove charge from a data storage structure of the memory cell.

3 . The memory of claim 2 , wherein the controller is further configured to cause the memory to apply the voltage level to the control gate of the memory cell before the voltage level applied to the data line reaches the predetermined voltage level.

4 . The memory of claim 1 , further comprising:
wherein the controller being configured to cause the memory to increase the voltage level applied to the data line during the first period of time comprises the controller being configured to cause the memory to increase the voltage level applied to the data line from ground to a first voltage level during the first period of time; wherein the controller being configured to cause the memory to decrease the voltage level applied to the control gate of the transistor during the first period of time comprises the controller being configured to cause the memory to decrease the voltage level applied to the control gate of the transistor from ground to a second voltage level during the first period of time; and wherein a magnitude of a voltage differential between the first voltage level and the second voltage level is equal to a desired offset for generating GIDL (gate-induced drain leakage) for an erase operation of the memory.

5 . The memory of claim 4 , wherein the transistor is a first transistor, and wherein the controller is further configured to cause the memory to:
maintain a voltage level applied to a control gate of a second transistor connected between the common source and the string of series-connected memory cells at ground during the first period of time.

6 . The memory of claim 4 , wherein the controller is further configured to cause the memory to:
increase a voltage level applied to the common source from ground to the predetermined voltage level while increasing the voltage level applied to the data line from ground to the predetermined voltage level; and in response to a magnitude of a voltage differential between the voltage level applied to the common source and ground being equal to the desired offset, increase the voltage level applied to the control gate of the second transistor at a same rate as increasing the voltage level applied to the common source.

7 . A memory, comprising:
an array of memory cells comprising a plurality of strings of series-connected memory cells; a plurality of data lines, wherein each data line of the plurality of data lines is selectively connected to a respective subset of strings of series-connected memory cells of the plurality of strings of series-connected memory cells; a common source selectively connected to each string of series-connected memory cells of the plurality of strings of series-connected memory cells; and a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
increase a voltage level applied to a data line of the plurality of data lines from a first voltage level to a second voltage level higher than the first voltage level and decrease a voltage level applied to a control gate of a transistor connected between the data line and a string of series-connected memory cells of its respective subset of strings of series-connected memory cells from the first voltage level to a third voltage level lower than the first voltage level;
increase the voltage level applied to the data line at a predetermined rate from the second voltage level while increasing the voltage level applied to the control gate of the transistor at the predetermined rate from the third voltage level; and
in response to the voltage level applied to the data line reaching a predetermined voltage level, ceasing increasing the voltage level applied to the data line and ceasing increasing the voltage level applied to the control gate of the transistor.

8 . The memory of claim 7 , wherein the controller is further configured to cause the memory to:
while the voltage level applied to the data line is at the predetermined voltage level, apply a voltage level to a control gate of a memory cell of the string of series-connected memory cells expected to remove charge from a data storage structure of the memory cell in conjunction with the predetermined voltage level applied to the data line.

9 . The memory of claim 8 , wherein the controller is further configured to cause the memory to apply the voltage level to the control gate of the memory cell before applying the predetermined voltage level to the data line.

10 . The memory of claim 7 , wherein the transistor connected between the data line and the string of series-connected memory cells comprises a GIDL (gate-induced drain leakage) generator gate.

11 . The memory of claim 7 , wherein the controller being configured to cause the memory to increase the voltage level applied to the data line at the predetermined rate comprises the controller being configured to cause the memory to increase the voltage level applied to the data line at a constant rate.

12 . The memory of claim 7 , wherein the transistor is a first transistor, and wherein the controller is further configured to cause the memory to:
maintain a voltage level applied to a control gate of a second transistor connected between the common source and the string of series-connected memory cells at the first voltage level while increasing the voltage level applied to the data line from the first voltage level to the second voltage level and while decreasing the voltage level applied to the control gate of the first transistor from the first voltage level to the third voltage level.

13 . The memory of claim 12 , wherein a magnitude of a voltage differential between the second voltage level and the third voltage level is equal to a desired offset for generating GIDL (gate-induced drain leakage) for an erase operation of the memory, and wherein the controll

Assignees

• Micron Technology Inc

Inventors

• Paolucci Giovanni Maria
• Tessariol Paolo
• Camerlenghi Emilio
• Carnevale Gianpietro
• Benvenuti Augusto

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title