Methods and apparatus for processing instructions

Patent metadata

Field	Value
Publication number	US-2025138827-A1
Application number	US-202418927890-A
Country	US
Kind code	A1
Filing date	Oct 26, 2024
Priority date	Oct 31, 2023
Publication date	May 1, 2025
Grant date	—

Abstract

A computer implemented method for processing instructions in a multiprocessing apparatus comprises obtaining a first instruction of a first process; decoding the first instruction to detect a continuation indicator associated with the first instruction; determining whether or not to enforce the continuation indicator; and when it is determined to enforce the continuation indicator: continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process. The continuation may temporarily suppress a normal eviction process based on a fairness algorithm, for example.

First claim

1 . A computer implemented method for processing instructions in a multiprocessing apparatus, the method comprising:
obtaining a first instruction of a first process; decoding the first instruction to detect a continuation indicator associated with the first instruction; determining whether or not to enforce the continuation indicator; when it is determined to enforce the continuation indicator: continuing to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process.

2 . The method of claim 1 , wherein continuing comprises suppressing an algorithmically predetermined eviction.

3 . The method of claim 1 , comprising:
decoding, with a decoder component, the second instruction of the first process to detect a continuation indicator associated with the second instruction; determining, with the decoder component, whether or not to enforce the continuation indicator of the second instruction; and suppressing eviction of the first process from an instruction unit until completion of the second instruction and at least a next sequential third instruction of the process responsive to a detected continuation indicator when it is determined to enforce the continuation indicator of the second instruction.

4 . The method of claim 3 , further comprising,
receiving, at the instruction unit from a control unit, the first process; fetching, with a decoder component from the control unit, the first instruction for the first process.

5 . The method of claim 4 , further comprising: obtaining, from the control unit, additional information associated with the first instruction, where the additional information comprises one or more of: the position of the first instruction in cache;
the type of the current and next sequential second instruction; a termination condition; a dependency condition; a priority level for the first instruction.

6 . The method of claim 5 , comprising:
identifying an eviction point for the first instruction based on or in response to the additional information associated with the first instruction.

7 . The method of claim 6 , further comprising:
evicting the first process from the instruction unit at completion of the first instruction in response to the identified eviction point.

8 . The method of claim 1 , further comprising:
storing instructions of the first process and instructions of a second process in storage at a first pipeline stage; issuing, to a second pipeline stage, the instructions of the first and second processes in an interleaved instruction stream.

9 . The method according to claim 1 , wherein the determining detects an “always continue” indication and always continues to execute the first process until completion of the first instruction and at least a next sequential second instruction of the first process.

10 . The method of claim 1 , further comprising:
storing instructions of the first process in a first storage at a first pipeline stage; storing instructions of a second process in a second storage at the first pipeline stage; selecting instructions from the first and/or second storage; issuing, to a second pipeline stage, the selected instructions as an instruction stream for processing.

11 . The method of claim 6 , where evicting the first process from the instruction unit at completion of the first instruction comprises:
returning the first process to a work queue at the control unit for selection by a scheduler.

12 . The method of claim 3 , further comprising:
issuing, from the instruction unit, a work request to a client unit to perform the work request in accordance with the first instruction.

13 . The method of claim 1 , wherein when it is determined not to enforce the continuation indicator:
evicting the first process from the instruction unit at completion of the first instruction.

14 . The method of claim 1 , wherein when a continuation indicator is not detected:
evicting the first process from the instruction unit at completion of the first instruction.

15 . The method of claim 13 , comprising:
receiving, from the control unit, a further process when the first process is evicted.

16 . The method of claim 1 , where the continuation indicator is encoded in the instruction.

17 . The method of claim 1 , wherein at least one of the first and the second processes comprises a warp.

18 . A multiprocessing apparatus operable to process instructions, comprising:
a receiver component for obtaining a first instruction of a first process; a decoder component to decode a first instruction of a first process to detect a continuation indicator associated with the first instruction and to determine whether or not to enforce the continuation indicator thereof; an eviction suppressor component to, when it is determined to enforce the continuation indicator, suppress eviction of the first process from the instruction unit to continue processing until completion of the first instruction and at least a next second sequential instruction of the first process.

19 . A computer program comprising computer program code to, when loaded into a processor and executed thereon, cause the processor to perform the method of claim 1 .

20 . A computer program operable to adapt a host processing system to provide an execution environment permitting operation of non-native processor instructions to perform the method of claim 1 .

Assignees

• Advanced Risc Mach Ltd

Inventors

• Robson John David
• Fielding Edvard
• Rajkumar Kalyani
• Watts Philip Michael

Classifications

• G06F9/3877

  using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12) · CPC title

• G06F9/3818

  Decoding for concurrent execution · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/3009 Primary

  Thread control instructions · CPC title

• G06F9/3802 Primary

  Instruction prefetching · CPC title