Memory device

Patent metadata

Field	Value
Publication number	US-2025126810-A1
Application number	US-202418734650-A
Country	US
Kind code	A1
Filing date	Jun 5, 2024
Priority date	Oct 13, 2023
Publication date	Apr 17, 2025
Grant date	—

Abstract

A memory device is provided. The memory device includes: a plurality of sub-array regions arranged spaced apart in a first and second horizontal directions, and each sub-array region including a plurality of memory cells, the first horizontal direction crossing the second horizontal direction; a dummy region disposed between the plurality of sub-array regions, the dummy region including a first metal pattern extending in the first horizontal direction at a first layer, a first lower contact extending in a vertical direction on a first portion of the first metal pattern, and a second lower contact extending in the vertical direction on a second portion of the first metal pattern; and a peripheral circuit region including a first upper contact connected to the first lower contact, a first circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second circuit connected to the second upper contact.

First claim

1 . A memory device comprising:
a plurality of sub-array regions arranged spaced apart in a first horizontal direction and a second horizontal direction, and each sub-array region comprising a plurality of memory cells, the first horizontal direction crossing the second horizontal direction; a dummy region disposed between the plurality of sub-array regions, the dummy region comprising a first metal pattern extending in the first horizontal direction at a first layer, a first lower contact extending in a vertical direction on a first portion of the first metal pattern, and a second lower contact extending in the vertical direction on a second portion of the first metal pattern; and a peripheral circuit region comprising a first upper contact connected to the first lower contact, a first circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second circuit connected to the second upper contact.

2 . The memory device of claim 1 , wherein the dummy region further comprises:
a second metal pattern adjacent the first metal pattern and extending in the first horizontal direction; a first via contact disposed on the second metal pattern and extending in the vertical direction; a third metal pattern in contact with the first via contact at a second layer and extending in the second horizontal direction; a third lower contact disposed on the second metal pattern and extending in the vertical direction; and a fourth lower contact disposed on the third metal pattern and extending in the vertical direction, and
wherein the peripheral circuit region further comprises:
a third upper contact connected to the third lower contact;
a third circuit connected to the third upper contact;
a fourth upper contact connected to the fourth lower contact; and
a fourth circuit connected to the fourth upper contact.

3 . The memory device of claim 2 , wherein a resistance of the first metal pattern is less than a resistance of at least one of the second metal pattern and the third metal pattern.

4 . The memory device of claim 1 , wherein the dummy region further comprises:
a fourth metal pattern extending in the first horizontal direction at a second layer; a second via contact disposed on the fourth metal pattern and extending in the vertical direction; a fifth metal pattern in contact with the second via contact at a third layer, and extending in the second horizontal direction; a fifth lower contact disposed on the fourth metal pattern and extending in the vertical direction; and a sixth lower contact disposed on the fifth metal pattern and extending in the vertical direction, and
wherein the peripheral circuit region further comprises:
a fifth upper contact connected to the fifth lower contact;
a first test circuit connected to the fifth upper contact;
a sixth upper contact connected to the sixth lower contact; and
a second test circuit connected to the sixth upper contact.

5 . The memory device of claim 4 , wherein a resistance of the first metal pattern is less than a resistance of at least one of the fourth metal pattern and the fifth metal pattern.

6 . The memory device of claim 1 , wherein the dummy region further comprises:
a first power metal pattern extending in the first horizontal direction at a second layer; a seventh lower contact disposed on the first power metal pattern and extending in the vertical direction; a second power metal pattern extending in the second horizontal direction at a third layer; and an eighth lower contact disposed on the second power metal pattern and extending in the vertical direction, and
wherein the peripheral circuit region further comprises:
a seventh upper contact connected to the seventh lower contact;
a first power circuit connected to the seventh upper contact;
an eighth upper contact connected to the eighth lower contact; and
a second power circuit connected to the eighth upper contact.

7 . The memory device of claim 1 , wherein the first lower contact comprises:
a first contact metal pattern disposed on the first portion of the first metal pattern and extending toward the peripheral circuit region; and a first contact pad disposed between the first contact metal pattern and the first upper contact, and
wherein the second lower contact comprises:
a second contact metal pattern disposed on the second portion of the first metal pattern and extending toward the peripheral circuit region; and
a second contact pad disposed between the second contact metal pattern and the second upper contact.

8 . The memory device of claim 7 , wherein the first upper contact comprises:
at least one third contact metal pattern in contact with the first circuit and extending toward the dummy region; and a third contact pad disposed between the at least one third contact metal pattern and the first contact pad, and
wherein the second upper contact comprises:
at least one fourth contact metal pattern in contact with the second circuit and extending toward the dummy region; and
a fourth contact pad disposed between the at least one fourth contact metal pattern and the second contact pad.

9 . A memory device comprising:
a plurality of sub-array regions each comprising a plurality of memory cells; a dummy region adjacent the plurality of sub-array regions, the dummy region comprising a first power metal pattern extending in a first horizontal direction at a first layer, a first lower contact extending in a vertical direction on the first power metal pattern, a second power metal pattern extending in a second horizontal direction at a second layer, and a second lower contact extending in the vertical direction on the second power metal pattern; and a peripheral circuit region comprising a first upper contact connected to the first lower contact, a first power circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second power circuit connected to the second upper contact.

10 . The memory device of claim 9 , wherein the dummy region further comprises:
a first metal pattern extending in one of the first horizontal direction and the second horizontal direction at a third layer; a third lower contact disposed on a first portion of the first metal pattern and extending in the vertical direction; and a fourth lower contact disposed on a second portion of the first metal pattern and extending in the vertical direction, and
wherein the peripheral circuit region further comprises:
a third upper contact connected to the third lower contact;
a first circuit connected to the third upper contact;
a fourth upper contact connected to the fourth lower contact; and
a second circuit connected to the fourth upper contact.

11 . The memory device of claim 10 , wherein the dummy region further comprises:
a second metal pattern adjacent the first metal pattern in the third layer and extending in the first horizontal direction; a first via contact disposed on the second metal pattern and extending in the vertical direction; a third metal pattern in contact with the first via contact at a fourth layer and extending in the second horizontal direction; a fifth lower contact disposed on the second metal pattern and extending in the vertical direction; and a sixth lower contact disposed on the third metal pattern and extending in the vertical direction, and
wherein the peripheral circuit region further comprises:
a fifth upper contact connected to the fifth lower contact;
a third circuit connected to the fifth upper contact;
a sixth upper contact connected to the sixth

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Changyoung
• Jung Sanghoon
• Park Youngseok
• Yoo Changsik

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10B80/00 Primary

  Assemblies of multiple devices comprising at least one memory device covered by this subclass · CPC title

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title