Rank-based dot product circuitry

Patent metadata

Field	Value
Publication number	US-2025123804-A1
Application number	US-202419002465-A
Country	US
Kind code	A1
Filing date	Dec 26, 2024
Priority date	Dec 23, 2019
Publication date	Apr 17, 2025
Grant date	—

Abstract

Integrated circuits with dot product circuitry are provided. The dot product circuitry may be configured to generate partial products of different ranks based on the inputs. The partial products may be organized into corresponding groups based on their ranks. Each group of partial products having the same rank can then be compressed using a compressor/reduction tree. At least some of the compressed partial product values may be shifted between the different groups to maintain the proper offset. Each partial product may have an associated one's to two's complement conversion bit. The conversion bits of the various partial product groups can be separately aggregated and then injected into the compressor tree at one or more locations.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
a partial product generation circuit to receive input operands and output corresponding partial products; a first compressor circuit to receive a first group of the partial products all having a first rank and output first vectors; a second compressor circuit to receive a second group of the partial products all having a second rank different from the first rank and output second vectors; and an adder circuit to output a dot product value based at least in part on the first vectors and the second vectors.

2 . The integrated circuit device of claim 1 , wherein the first group of partial products and the second group of partial products are grouped based at least in part on a respective rank.

3 . The integrated circuit device of claim 1 , wherein the first compressor circuit compresses the first group of the partial products without shifting, and wherein the second compressor circuit compresses the second group of partial products without shifting.

4 . The integrated circuit device of claim 3 , comprising a third compressor circuit to receive the first vectors and the second vectors and output third vectors, wherein the second vectors are shifted relative to the first vectors by first shifting circuitry.

5 . The integrated circuit device of claim 4 , comprising a fourth compressor circuit to receive the third vectors and fourth vectors from a fifth compressor circuit, wherein the fourth vectors are shifted relative to the third vectors by second shifting circuitry.

6 . The integrated circuit device of claim 5 , comprising a multiplexer to selectively bypass the second shifting circuit to support a plurality of input precisions.

7 . The integrated circuit device of claim 1 , wherein a bit width of a first vector of the first vectors is one bit greater than the bit width of a partial product of the first group of the partial products.

8 . The integrated circuit device of claim 1 , comprising a multiplexer to selectively bypass a shifting circuit.

9 . The integrated circuit device of claim 1 , wherein the integrated circuit device comprises a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), an application specific standard product (ASSP), or any combination thereof.

10 . An integrated circuit comprising:
a plurality of compressor circuits to respectively compress a group of partial products all having the same rank and output a plurality of vectors, wherein the group of partial products are grouped based on rank and not shifted prior to compression; and at least one adder to output a sum of the plurality of vectors.

11 . The integrated circuit of claim 10 , comprising at least one shifting circuit to shift a group of vectors of the plurality of vectors.

12 . The integrated circuit of claim 10 , comprising a multiplexer to selectively bypass a shifting circuit.

13 . The integrated circuit of claim 10 , comprising:
a first one's complement to two's complement conversion bit aggregation circuit to inject at least one vector to a compressor circuit of the plurality of compressor circuits; and a second one's complement to two's complement conversion bit aggregation circuit to inject at least one additional vector to the compressor circuit, wherein a precision of the at least one vector is different from the precision of the at least one additional vector.

14 . The integrated circuit of claim 13 , comprising a multiplexer to select only the first one's to two's complement conversion bit aggregation circuit during a first precision mode and select only the second one's to two's complement conversion bit aggregation circuit during a second precision mode.

15 . The integrated circuit of claim 10 , wherein the plurality of compressor circuits comprises:
a first compressor circuit to compress a first group of partial products all having a first rank into first vectors of the plurality of vectors; and a second compressor circuit to compress a second group of partial products all having a second rank into second vectors of the plurality of vectors, wherein the first rank is different from the second rank.

16 . An application-specific integrated circuit (ASIC) comprising:
a first compressor circuit to receive a first group of partial products all having a first rank and output first vectors; a second compressor circuit to receive a second group of partial products all having a second rank different from the first rank and output second vectors; a first shifting circuit to shift the second vectors relative to the first vectors; and a third compressor circuit to compress the first vectors and the shifted second vectors and output third vectors.

17 . The ASIC of claim 16 , comprising:
a second shifting circuit to shift fourth vectors from a fourth compressor circuit relative to the third vectors; and a fourth compressor circuit to compress the third vectors and the shifted fourth vectors and output fifth vectors.

18 . The ASIC of claim 17 , comprising a multiplexer to bypass the second shifting circuit.

19 . The ASIC of claim 17 , comprising an adder to output a sum based at least in part on the fifth vectors and sixth vectors from a fifth compressor circuit.

20 . The ASIC of claim 16 , wherein the first compressor circuit compresses the first group of partial products without shifting, and wherein the second compressor circuit compresses the second group of partial products without shifting.

Assignees

• Altera Corp

Inventors

• Langhammer Martin

Classifications

• G06F7/5336

  overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm · CPC title

• G06F7/523 Primary

  Multiplying only · CPC title

• G06F7/5443 Primary

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title