Semiconductor device including gate contact structure formed from gate structure

Patent metadata

Field	Value
Publication number	US-2025120183-A1
Application number	US-202418954980-A
Country	US
Kind code	A1
Filing date	Nov 21, 2024
Priority date	Oct 5, 2023
Publication date	Apr 10, 2025
Grant date	—

Abstract

Provided is a semiconductor device which may include: a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate structure.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate structure.

2 . The semiconductor device of claim 1 , wherein the gate contact structure comprises a protrusion on a top surface of the gate structure;

3 . The semiconductor device of claim 2 , wherein the gate structure comprises a gate dielectric layer, a work-function metal layer, and a gate electrode, and
wherein a surface from which the protrusion begins to protrude is at a level above a top surface of the work-function metal layer.

4 . The semiconductor device of claim 3 , wherein a surface from which the protrusion begins to protrude is at a level of a top surface of the work-function metal layer.

5 . The semiconductor device of claim 1 , wherein the gate structure comprises a gate dielectric layer, a work-function metal layer, and a gate electrode, and
wherein the gate contact structure is a portion of the gate electrode itself.

6 . The semiconductor device of claim 1 further comprising a gate capping structure on at least a lateral side of the gate contact structure.

7 . The semiconductor device of claim 1 , wherein the channel structure comprises a 1 st channel structure at a 1 st level and a 2 nd channel structure at a 2 nd level above the 1 st level,
wherein the gate structure comprises a 1 st work-function metal layer and a 2 nd work-function metal layer respectively on the 1 st channel structure and the 2 nd channel structure, wherein the gate structure further comprises a gate electrode on at least the 2 nd work-function metal layer, and wherein the gate contact structure is a portion of the gate electrode itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate electrode.

8 . The semiconductor device of claim 7 , wherein the gate electrode is shared by a 1 st transistor comprising the 1 st channel structure and a 2 nd transistor comprising the 2 nd channel structure.

9 . The semiconductor device of claim 1 , wherein a top surface of the gate structure is not substantially flat or plain.

10 . A semiconductor device comprising:
a channel structure; a gate structure on the channel structure; and a gate contact structure on the gate structure, the gate contact structure configured to receive a gate input signal, wherein the gate contact structure is a portion of the gate structure itself, and wherein the gate contact structure comprises a protrusion on a top surface of the gate structure.

11 . The semiconductor device of claim 10 , wherein the gate structure comprises a gate dielectric layer, a work-function metal layer, and a gate electrode, and
wherein the top surface of the gate structure is a surface of the gate electrode.

12 . The semiconductor device of claim 10 , wherein the gate structure comprises a gate dielectric layer, a work-function metal layer, and a gate electrode, and
wherein the gate contact structure is a portion of the gate electrode.

13 . The semiconductor device of claim 12 , wherein a surface from which the protrusion begins to protrude is at a level above a top surface of the work-function metal layer.

14 . The semiconductor device of claim 10 , wherein the channel structure comprises a 1 st channel structure at a 1 st level and a 2 nd channel structure at a 2 nd level above the 1 st level,
wherein the gate structure comprises a 1 st work-function metal layer and a 2 nd work-function metal layer respectively on the 1 st channel structure and the 2 nd channel structure, wherein the gate structure further comprises a gate electrode on at least the 2 nd work-function metal layer, and wherein the gate contact structure is a portion of the gate electrode itself, and no connection surface, interface or boundary is formed between the gate contact structure and the gate electrode.

15 . The 3D-stacked semiconductor device of claim 10 , wherein a top surface of the gate structure is not substantially flat or plain.

16 . A method of manufacturing a semiconductor device, the method comprising:
forming a gate structure such that the gate structure comprises a protrusion and a remaining portion of the gate structure, the protrusion protruding from a top surface of the remaining portion of the gate structure; and connecting a metal line and the protrusion, wherein the protrusion and the remaining portion of the gate structure do not have a connection surface, interface or boundary therebetween.

17 . The method of claim 16 , wherein the gate structure comprises a gate dielectric layer, a work-function metal layer, and a gate electrode, and
wherein the protrusion is a portion of the gate electrode.

18 . The method of claim 17 , wherein a surface from which the protrusion begins to protrude is at a level above a top surface of the work-function metal layer.

19 . The method of claim 17 , wherein a surface from which the protrusion begins to protrude is at a level of a top surface of the work-function metal layer.

20 . The method of claim 17 . wherein a top surface of the remaining portion of the gate structure comprises a top surface of the work-function metal layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Myunghoon
• Lee Jaehong
• Yun Seungchan
• Seo Kang-Ill

Classifications

• H10D84/83138

  the IGFETs characterised by having different shapes or dimensions of their gate conductors · CPC title

• H10D84/851

  comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D84/0142

  the gate conductors having different shapes or dimensions · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D30/019

  of FETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title