Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2025118594-A1
Application number	US-202318377513-A
Country	US
Kind code	A1
Filing date	Oct 6, 2023
Priority date	Oct 6, 2023
Publication date	Apr 10, 2025
Grant date	—

Abstract

The semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a first dielectric layer, a first metal layer, a second metal layer, a first etching stop layer, a second etching stop layer, a second dielectric layer, a first via and a second via. The first metal layer and the second metal are embedded in the first dielectric layer. The first etching stop layer is disposed on the first dielectric layer. The second etching stop layer is disposed on the first etching stop layer. The second dielectric layer is disposed on the second etching stop layer. The first via and the second via are embedded in the second dielectric layer. A width of the second etching stop layer is smaller a width of the first etching stop layer.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a first dielectric layer; a first metal layer, embedded in the first dielectric layer; a second metal layer, embedded in the first dielectric layer and separated from the first metal layer, wherein the first dielectric layer exposes the first metal layer and the second metal layer; a first etching stop layer, disposed on the first dielectric layer; a second etching stop layer, disposed on the first etching stop layer; a second dielectric layer, disposed on the second etching stop layer; a first via, embedded in the second dielectric layer and electrically connected to the first metal layer; and a second via, embedded in the second dielectric layer, separated from the first via and electrically connected to the second metal layer, wherein a width of the second etching stop layer is smaller a width of the first etching stop layer.

2 . The semiconductor structure according to claim 1 , wherein the second etching stop layer is disposed between the first via and the second via.

3 . The semiconductor structure according to claim 1 , wherein a material of the second etching stop layer is different from a material of the second etching stop layer.

4 . The semiconductor structure according to claim 1 , wherein the first dielectric layer is fully covered by the first etching stop layer.

5 . The semiconductor structure according to claim 1 , wherein a thickness of the first etching stop layer is 1 nm to 100 nm.

6 . The semiconductor structure according to claim 1 , wherein a thickness of the second etching stop layer is 1 nm to 100 nm.

7 . The semiconductor structure according to claim 1 , wherein a thickness of a combination of the first etching stop layer and the second etching stop layer is 1 nm to 200 nm.

8 . A manufacturing method of a semiconductor structure, comprising:
forming a first dielectric layer, a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer are embedded in the first dielectric layer and are separated from each other; forming a blocking layer on the first metal layer and the second metal layer; selectively depositing a first etching stop layer on the first dielectric layer by using the blocking layer as a mask; removing the blocking layer and depositing a second etching stop layer on the first metal layer, the second metal layer and the first etching stop layer; forming a second dielectric layer on the second etching stop layer; etching the second dielectric layer to form a first concave and a second concave; and forming a first via and a second via in the first concave and the second concave respectively.

9 . The manufacturing method of the semiconductor structure according to claim 8 , wherein a material of the blocking layer is a polymer inhibitor composed of C, O, N, Cl or F, a self-assembly monolayer composed of phosphonic acid material, thiol material or silane-based material, benzotriazole (BTA), thiol (—SH) material, or phosphonic acid (—POOH) material.

10 . The manufacturing method of the semiconductor structure according to claim 8 , wherein in the step of forming the blocking layer, the blocking layer is formed by vapor atomic layer deposition (ALD), monolayer doping (MLD), chemical vapor deposition (CVD), spin coating, dipping, or spray.

11 . The manufacturing method of the semiconductor structure according to claim 8 , wherein in the step forming the blocking layer, the first metal layer and the second metal is pre-cleaned.

12 . The manufacturing method of the semiconductor structure according to claim 8 , wherein in the step forming the blocking layer, the blocking layer is cured at 10° C. to 450° C.

13 . The manufacturing method of the semiconductor structure according to claim 8 , wherein in the step of removing the blocking layer, the blocking layer is removed by thermal annealing, plasma treatment or wet approach.

14 . A semiconductor structure, comprising:
a first dielectric layer; a first metal layer, embedded in the first dielectric layer; a second metal layer, embedded in the first dielectric layer and separated from the first metal layer, wherein the first dielectric layer exposes the first metal layer and the second metal layer; a first etching stop layer, disposed on the first dielectric layer; a second etching stop layer, disposed on the first etching stop layer; a second dielectric layer, disposed on the second etching stop layer; a first via, embedded in the second dielectric layer, and electrically connected to the first metal layer; and a second via, embedded in the second dielectric layer, separated from the first via and electrically connected to the second metal layer, wherein a width of the first via is larger than a width of the first metal layer.

15 . The semiconductor structure according to claim 14 , wherein a width of the second etching stop layer is smaller a width of the first etching stop layer.

16 . The semiconductor structure according to claim 14 , wherein a material of the second etching stop layer is different from a material of the second etching stop layer.

17 . The semiconductor structure according to claim 14 , wherein the first dielectric layer is fully covered by the first etching stop layer.

18 . The semiconductor structure according to claim 14 , wherein a thickness of the first etching stop layer is 1 nm to 100 nm.

19 . The semiconductor structure according to claim 14 , wherein a thickness of the second etching stop layer is 1 nm to 100 nm.

20 . The semiconductor structure according to claim 14 , wherein a thickness of a combination of the first etching stop layer and the second etching stop layer is 1 nm to 200 nm.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Su Chia-Wei
• Chen Hsin-Ping
• Wu Yung-Hsu
• Su Li-Ling
• Liao Chan-Yu
• Lee Shao-Kuan
• Lo Ting-Ya
• Huang Hsin-Yen
• Chang Hsiao-Kang

Classifications

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/075 Primary

  of multilayered thin functional dielectric layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title